| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-12-17 | Remove some printlns in tests (#2445) | Jack Koenig | |
| Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | |||
| 2021-09-29 | Add RTLIL Backend. (#2331) | Nicolas Machado | |
| * Added RTLIL Backend. * Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing. * Fix build on scala 2.13 * Add additional equivalence test, make some bugfixes and perf opts to the emitter. * Final changes as requested by Kevin, code cleanup, add support for formal cells. | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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