| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-03-19 | Legalize neg: -x becomes 0 - x (#2128) | Jack Koenig | |
| This fixes an error with negating a negative SInt literal and a [debatable] lint warning in Verilator when negating any value. This behavior matches that of Chisel (which directly emits the 0 - x already). | |||
| 2020-09-16 | Change to Apache 2.0 License (#1901) | Chick Markley | |
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson | |
| * Rename implict module "clk" input to "clock". This doesn't rename all the "self-contained" test instances. nor the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. * Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances. This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. | |||
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig | |
| Replace with more sensible comment to see LICENSE rather than including the whole license in every file | |||
| 2016-09-12 | Add LegalizeSpec for testing Verilog Legalization pass | Jack | |
| 2016-05-03 | Add Expand Whens test | jackkoenig | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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