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* Use signed output in LargeParamExecutionTest
Change the Verilog used in LargeParamExecutionTest to match its
ExtModule specification. An ExtModule with an SInt port should map to
a separate Verilog module with a signed port and this is disjoint from
an ExtModule with a UInt port.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Error on ExtModules w/ same defname, diff. ports
Adds a high form check to ensure that external modules that have the
same defname also have exactly the same ports.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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