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2016-09-07put InferWidths in a seperate file and fix spacesDonggyu Kim
2016-09-07refactor checksDonggyu Kim
2016-09-07clean up PrimOpsDonggyu Kim
2016-09-07clean up miscsDonggyu Kim
2016-09-07clean up WIR.scalaDonggyu Kim
2016-09-07Merge branch 'master' into cleanup_passesAdam Izraelevitz
2016-09-07clean up Emitter.scala (#275)Donggyu
2016-09-07clean up SplitExpressionsDonggyu Kim
2016-09-07clean up LowerTypesDonggyu Kim
2016-09-07clean up PullMuxes & ExpandConnectsDonggyu Kim
2016-09-07clean up Utils.scalaDonggyu Kim
remove unnecessary functions & change spaces
2016-09-07remove Utils.ONEDonggyu Kim
2016-09-07remove Utils.tpeDonggyu Kim
2016-09-07Utils.scala: remove vars with foldDonggyu Kim
2016-09-07Added ReplaceSubAccesses before RemoveSubAccessesazidar
2016-09-07add caches for create_exps in RemoveAccessDonggyu Kim
2016-09-07clean up RemoveAccessesDonggyu Kim
2016-09-06optimize equals of WrappedExpression & WrappedTypeDonggyu Kim
2016-09-06remove unnecessary mappers in NamespaceDonggyu Kim
there's a big stack overhead with mappers
2016-09-06replace flatMap with foldLeft in create_expsDonggyu Kim
internal implementation for flatMap seems to be inefficient
2016-09-06Address style feedback and add tests for getConnectOrigin utilityAngie
2016-09-06Support optionally filling write mask to data width via transform input ↵Angie
config file
2016-09-06Expanded annotations for valid memory sizesAngie
2016-09-06Edited conf generation to handle mem namespace collisionAngie
* Also started separate pass for annotating valid memory
2016-09-06Made the connect origin function more powerfulAngie
* It analyzes through statements that ConstProp would've optimized * Edge case wmask can be removed (pass tries harder to figure out that wmask = wen)
2016-09-06Added simple unit test for ReplSeqMemAngie
2016-09-06Added back support for conf writing.Angie
* Conf file info is passed in through annotations. * A pass should have its own set of sub-arguments delimited by :
2016-09-06Changed wmask to convert from VecType to UIntAngie
* Instead of filling the whole data width * Added helper functions in MemUtils
2016-09-06Replace DefMemories with wrapped black boxAngie
* Note, this version uses Albert's toBitMask function, * which expands the bit mask to be the full data width (similar to Chisel2 output) * Black boxes only have wmasks as needed
2016-09-06Pulled out duplicate memory annotationsAngie
* Annotate reference * Changed memory port names to RWx, Wx, Rx, etc. and reconnected nodes
2016-09-06Corrected counting for VectorTypes in MemUtilsAngie
* Was originally adding one extra set of things (to -> until) * MemPortUtil conditionally includes wmask, if necessary Changed endian-ness of write data/mask to match convention (little endian)
2016-09-06Pulled out memory annotation (write mask)Angie
* Annotates all sequential memories that can be black boxed. * Annotates sequential memories that don't need write masks.
2016-09-06Generated *.conf file for unique sramsAngie
2016-09-06Minor utility changes.Angie
* Corrected names to match current RW port spec * Added Jack's Namespace on Circuit
2016-09-06Added starter code for SMem replacementAngie
2016-09-05Change null statement to empty begin end (#264)Colin Schmidt
this eliminates warnings in recent versions of VCS
2016-08-25emit wires instead of registers for invalid randomizationHoward Mao
Before, the verilog emitter would connect registers to the invalid ports and use random initialization on the generated registers. It is better to generate wires instead and use random assignment on the wires.
2016-08-25Finer grained control over randomizationHoward Mao
We previously had `ifdef guards on some parts of the emitted verilog to control whether some registers or nets should be given random initial values. These guards were all dependent on the RANDOMIZE macro. However, there were actually three separate cases being controlled 1. Giving random values to disconnected wires 2. Random initialization of registers 3. Random initialization of memories It is possible that the designer would want to switch these three on or off independently in simulation. For instance, the latter two are usually safe because registers and memories will get some definite binary value at power on in the actual circuit, but the first one can be quite dangerous because the undriven wire could be metastable. This change provides separate macros for each of the three sets of guards so that they can be controlled independently.
2016-08-18emit correct enable signals for memories (#242)Donggyu
2016-08-18Add MemUtils to aid in interfacing with alternate memory implementations (#244)Albert Magyar
2016-08-18Remove redundant test and errors.append() in check_types_e(). (#243)Jim Lawson
2016-08-17Change RW port names (#236)Angie Wang
* Updated FIRRTL spec + related code for readwrite ports. (write) data -> wdata & mask -> wmask for clarity * Also removed simple.fir that snuck into master branch.
2016-08-17Fixed cmdline usage string (#235)Adam Izraelevitz
Now prints usage when given incorrect arguments
2016-08-15Remove stanza (#231)Adam Izraelevitz
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-08-12Fix calculation of runtime for ANTLR Parser (#229)Jack Koenig
2016-08-12Add missing case for connecting ClockTypeMegan Wachs
2016-08-09provide parser for naive string (#227)Donggyu
2016-08-09fix read port enables in RemoveCHIRRTLDonggyu Kim
read port enables for cmems should always be high
2016-08-08Don't create output files until the compiler succeedsAndrew Waterman
Creating the output file preemptively screws up make, as on subsequent executions of make, it thinks the task succeeded.
2016-08-05Merge pull request #220 from ucb-bar/fix-width-error-msgAdam Izraelevitz
Bugfix: recursing stmts to remove unknown widths
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