diff options
| author | Adam Izraelevitz | 2016-08-05 13:18:14 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-05 13:18:14 -0700 |
| commit | fa0573f657f722b1a163ce721f06172a1a9782c2 (patch) | |
| tree | 7f56fce5cbecf29dd56d189bed6746c9e6173f19 /src/main | |
| parent | 732d0c6ccbcb971abfde4679a27384647d18b44d (diff) | |
| parent | 6aea3924fb48cbb4c1be217630c60be39b243ff1 (diff) | |
Merge pull request #220 from ucb-bar/fix-width-error-msg
Bugfix: recursing stmts to remove unknown widths
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/passes/Checks.scala | 9 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/Passes.scala | 2 |
2 files changed, 10 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala index 7350a8c1..8c94d737 100644 --- a/src/main/scala/firrtl/passes/Checks.scala +++ b/src/main/scala/firrtl/passes/Checks.scala @@ -690,6 +690,9 @@ object CheckWidths extends Pass { s"$info : [module $mname] Width too small for constant " + serialize(b) + ".") class NegWidthException(info:Info) extends PassException(s"${info}: [module ${mname}] Width cannot be negative or zero.") + class BitsWidthException(info: Info, hi: BigInt, width: BigInt) extends PassException(s"${info}: [module ${mname}] High bit $hi in bits operator is larger than input width $width.") + class HeadWidthException(info: Info, n: BigInt, width: BigInt) extends PassException(s"${info}: [module ${mname}] Parameter $n in head operator is larger than input width $width.") + class TailWidthException(info: Info, n: BigInt, width: BigInt) extends PassException(s"${info}: [module ${mname}] Parameter $n in tail operator is larger than input width $width.") def run (c:Circuit): Circuit = { val errors = new Errors() def check_width_m (m:DefModule) : Unit = { @@ -720,6 +723,12 @@ object CheckWidths extends Pass { } check_width_w(info)(e.width) } + case DoPrim(Bits, Seq(a), Seq(hi, lo), _) if(long_BANG(a.tpe) <= hi) => + errors.append(new BitsWidthException(info, hi, long_BANG(a.tpe))) + case DoPrim(Head, Seq(a), Seq(n), _) if(long_BANG(a.tpe) < n) => + errors.append(new HeadWidthException(info, n, long_BANG(a.tpe))) + case DoPrim(Tail, Seq(a), Seq(n), _) if(long_BANG(a.tpe) <= n) => + errors.append(new TailWidthException(info, n, long_BANG(a.tpe))) case (e:DoPrim) => false case (e) => false } diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala index 135d00b3..478f5fd8 100644 --- a/src/main/scala/firrtl/passes/Passes.scala +++ b/src/main/scala/firrtl/passes/Passes.scala @@ -520,7 +520,7 @@ object InferWidths extends Pass { } def reduce_var_widths_s (s: Statement): Statement = { def onType(t: Type): Type = t map onType map reduce_var_widths_w - s map onType + s map reduce_var_widths_s map onType } val modulesx = c.modules.map{ m => { |