Merge pull request #220 from ucb-bar/fix-width-error-msg

Bugfix: recursing stmts to remove unknown widths

3 files changed, 67 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 7350a8c1..8c94d737 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -690,6 +690,9 @@ object CheckWidths extends Pass {
          s"$info : [module $mname]  Width too small for constant " +
          serialize(b) + ".")
    class NegWidthException(info:Info) extends PassException(s"${info}: [module ${mname}] Width cannot be negative or zero.")
+   class BitsWidthException(info: Info, hi: BigInt, width: BigInt) extends PassException(s"${info}: [module ${mname}] High bit $hi in bits operator is larger than input width $width.")
+   class HeadWidthException(info: Info, n: BigInt, width: BigInt) extends PassException(s"${info}: [module ${mname}] Parameter $n in head operator is larger than input width $width.")
+   class TailWidthException(info: Info, n: BigInt, width: BigInt) extends PassException(s"${info}: [module ${mname}] Parameter $n in tail operator is larger than input width $width.")
    def run (c:Circuit): Circuit = {
       val errors = new Errors()
       def check_width_m (m:DefModule) : Unit = {
@@ -720,6 +723,12 @@ object CheckWidths extends Pass {
                   }
                   check_width_w(info)(e.width)
                }
+               case DoPrim(Bits, Seq(a), Seq(hi, lo), _) if(long_BANG(a.tpe) <= hi) =>
+                 errors.append(new BitsWidthException(info, hi, long_BANG(a.tpe)))
+               case DoPrim(Head, Seq(a), Seq(n), _) if(long_BANG(a.tpe) < n) =>
+                 errors.append(new HeadWidthException(info, n, long_BANG(a.tpe)))
+               case DoPrim(Tail, Seq(a), Seq(n), _) if(long_BANG(a.tpe) <= n) =>
+                 errors.append(new TailWidthException(info, n, long_BANG(a.tpe)))
                case (e:DoPrim) => false
                case (e) => false
             }
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 135d00b3..478f5fd8 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -520,7 +520,7 @@ object InferWidths extends Pass {
       }
       def reduce_var_widths_s (s: Statement): Statement = {
         def onType(t: Type): Type = t map onType map reduce_var_widths_w
-        s map onType
+        s map reduce_var_widths_s map onType
       }
    
       val modulesx = c.modules.map{ m => {
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index bc8db897..2d1bbdc1 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -232,4 +232,61 @@ class UnitTests extends FirrtlFlatSpec {
      )
      executeTest(input, check, passes)
   }
+
+  "Oversized bit select" should "throw an exception" in {
+    val passes = Seq(
+      ToWorkingIR,
+      ResolveKinds,
+      InferTypes,
+      ResolveGenders,
+      InferWidths,
+      CheckWidths)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    node x = bits(UInt(1), 100, 0)""".stripMargin
+    intercept[CheckWidths.BitsWidthException] {
+      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+
+  "Oversized head select" should "throw an exception" in {
+    val passes = Seq(
+      ToWorkingIR,
+      ResolveKinds,
+      InferTypes,
+      ResolveGenders,
+      InferWidths,
+      CheckWidths)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    node x = head(UInt(1), 100)""".stripMargin
+    intercept[CheckWidths.HeadWidthException] {
+      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+
+  "Oversized tail select" should "throw an exception" in {
+    val passes = Seq(
+      ToWorkingIR,
+      ResolveKinds,
+      InferTypes,
+      ResolveGenders,
+      InferWidths,
+      CheckWidths)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    node x = tail(UInt(1), 100)""".stripMargin
+    intercept[CheckWidths.TailWidthException] {
+      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
 }