diff options
| author | Angie | 2016-08-19 19:38:51 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-09-06 00:17:17 -0700 |
| commit | 6eba1d0685f5ee383246eb0c3ec7c06ad413cb34 (patch) | |
| tree | 5ae55c625542cbaf73fd47e9020994d027fd8eab /src/main | |
| parent | 0d5fa689a45693bf6db9bc6d9dc3f150bc3ff4b8 (diff) | |
Minor utility changes.
* Corrected names to match current RW port spec
* Added Jack's Namespace on Circuit
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/Namespace.scala | 9 | ||||
| -rw-r--r-- | src/main/scala/firrtl/passes/MemUtils.scala | 4 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Namespace.scala b/src/main/scala/firrtl/Namespace.scala index 7d4758c5..93e0ec76 100644 --- a/src/main/scala/firrtl/Namespace.scala +++ b/src/main/scala/firrtl/Namespace.scala @@ -84,5 +84,14 @@ object Namespace { namespace } + + /** Initializes a [[Namespace]] for [[Module]] names in a [[Circuit]] */ + def apply(c: Circuit): Namespace = { + val namespace = new Namespace + c.modules foreach { m => + namespace.namespace += m.name + } + namespace + } } diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala index 4b91d9cd..263422df 100644 --- a/src/main/scala/firrtl/passes/MemUtils.scala +++ b/src/main/scala/firrtl/passes/MemUtils.scala @@ -148,9 +148,9 @@ object MemPortUtils { def rwPortToBundle(mem: DefMemory) = BundleType(Seq( Field("wmode", Default, UIntType(IntWidth(1))), - Field("data", Default, mem.dataType), + Field("wdata", Default, mem.dataType), Field("rdata", Flip, mem.dataType), - Field("mask", Default, create_mask(mem.dataType)), + Field("wmask", Default, create_mask(mem.dataType)), Field("addr", Default, UIntType(IntWidth(ceil_log2(mem.depth)))), Field("en", Default, UIntType(IntWidth(1))), Field("clk", Default, ClockType))) |