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2016-09-21refactor AnnotateValidMemConfigsDonggyu Kim
2016-09-21refactor ReplaceMemMacrosDonggyu Kim
2016-09-21refactor UpdateDuplicateMemMacrosDonggyu Kim
2016-09-21clean up ReplSeqMemDonggyu Kim
2016-09-21refactor AnnotateMemMacrosDonggyu Kim
2016-09-21refactor InferReadWriteDonggyu Kim
2016-09-21generalize Analysis.getConnects for code resuseDonggyu Kim
2016-09-16fill empty module body with "begin end" (#305)Yunsup Lee
* fill empty module body with "begin end" apparently vivado treats an empty module as a black box and triggers an error * Changed empty module to use always @(*) begin end
2016-09-15Fix non-determinism bug in ExpandWhens (#303)Jack Koenig
Despite the fact that LinkedHashMaps preserve insertion order in traversal, it appears that .keys and .keySet return Sets that do not provide the same guarantee
2016-09-14fix spaces in WIR.scalaDonggyu Kim
2016-09-14style fixes for Compiler.scala, LoweringCompiler.scalaDonggyu Kim
2016-09-14Fix for more general case of getConnectOrigin with reg feedback (#301)Angie Wang
2016-09-14fix enable signal inferecne for smems' read ports (#289)Donggyu
2016-09-14Fixed infinite loop for finding connect origin in ReplSeqMem (#300)Angie Wang
* Addressed the fact that a node can be connected to itself (updating reg)
2016-09-13Fix a lurking width-inference bug; improve adjacent style (#298)Andrew Waterman
ceil(log(x) / log(2)) does not, in general, round to ceil(log2(x)). I noticed this because of #297.
2016-09-13use BoolType for UIntType(IntWidth(1))Donggyu Kim
2016-09-13remove VIndentDonggyu Kim
2016-09-13use case object for WVoid, WInvalidDonggyu Kim
2016-09-13cache IntWidths to avoid redudant object creationsDonggyu Kim
2016-09-13use case object for KindDonggyu Kim
2016-09-13clean up PadWidthDonggyu Kim
2016-09-13clean up LowerTypesDonggyu Kim
no vars for mname, info
2016-09-13clean up Passes.scalaDonggyu Kim
2016-09-13type aliasesDonggyu Kim
2016-09-13remove Utils.{width_BANG, long_BANG}Donggyu Kim
2016-09-13remove Utils.get_typeDonggyu Kim
2016-09-13use MemPortUtils.memType for DefMemoryDonggyu Kim
2016-09-13remove Utils.{mapr, get_name} and fix spacesDonggyu Kim
2016-09-13MemPortUtils: return correct memory typesDonggyu Kim
2016-09-13clean up MemUtilsDonggyu Kim
2016-09-12Add legalization of pad operation on literals.Jack
Performing a pad on SInt literals results in linting warnings in Verilator. This commit replaces pad operations on literal values with a literal of the correct width.
2016-09-12Cast bit select of SInt in PadWidths to SIntJack
Fixes #172
2016-09-12Legalize bit select. Run Legalize after PadWidths.Jack
Bit selecting a literal resulted in invalid Verilog. Legalize now deals with this by replacing any bits select of UInt or SInt literals with a new literal composed of the selected bits. Legalize also is now run after PadWidths because that pass introduces this issue. Fixes #170
2016-09-12Change Legalize Connect to respect SIntJack
Legalize will wrap the rhs of a connect statement with a bit select primop if the lhs is of smaller width than the rhs. This bit select is now wrapped in a asSInt cast if the original rhs was an SInt so that is has the correct type. Fixes #173
2016-09-12Change Legalize Shift Right to respect SIntjackkoenig
Fix bug where Legalize was generating a bit select for SInts without then casting to SInt Fixes #169
2016-09-12Change bitWidth to support ClockTypejackkoenig
Match on GroundType instead of UIntType and SIntType
2016-09-12Add unapply for GroundTypejackkoenig
2016-09-12Change Mappers to Value Classesjackkoenig
2016-09-12Rework map functions as class methodsjackkoenig
Changed code from match statements in Mappers.scala to methods on the various IR classes. This allows custom IR nodes to implement the mapper functions and thus work (ie. not match error) when map is called on them. This also should have a marginal performance increase because of use of virtual function calls rather than match statements.
2016-09-12Fixed bug where nodes of Invalids where createdazidar
2016-09-12Bug fix -- remove all empty expressions after ReplSeqMem passes (#294)Angie Wang
* Bug fix -- remove all empty expressions after ReplSeqMem passes * Added test to make sure ReplSeqMem can handle BundleType SMem (EmptyExpression leakage)
2016-09-08Revert Expand Whens to process a set of connection lhsjackkoenig
2016-09-08memoize nodes in ExpandWhensDonggyu Kim
2016-09-08remove Utils.{AND, OR, NOT, EQV}Donggyu Kim
hidden const props not desirable
2016-09-08clean up ExpandWhensDonggyu Kim
2016-09-08refactor RemoveCHIRRTLDonggyu Kim
2016-09-08refactor resolvesDonggyu Kim
2016-09-08refactor InferTypesDonggyu Kim
2016-09-08split Passes.scala into multiple files(InferTypes.scala, Resolves.scala, ↵Donggyu Kim
RemoveCHIRRTL.scala)
2016-09-08refactor InferWidthsDonggyu Kim
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