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Reset, AsyncReset, Interval, attach, assert, assume, and cover have all
been added as keywords but not added to the allowlist for parsing as
ids.
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Add a private pass, LegalizeConnectsOnly, that behaves like
LegalizeConnects, but only pads connects instead of connects and
register inits. Padding is necessary for ReplSeqMem, but ReplSeqMem
runs before LowerTypes and vector registers can still exist at this
point. Connects, conversely, are all blown out by ExpandConnects and
can be safely, blindly treated as ground type.
Fixes #2379.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* Demonstrate a couple failing cases
* Have TopWiring ignore unnamed declarations as potential sources
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* Have Flatten & InlineInstances remove their annotations
* Format
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* Added RTLIL Backend.
* Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing.
* Fix build on scala 2.13
* Add additional equivalence test, make some bugfixes and perf opts to the emitter.
* Final changes as requested by Kevin, code cleanup, add support for formal cells.
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This required also bumping sbt-scalafix to bring in a newer version of
semanticdb. The new version of semanticdb had an issue with a regex in
SMTLib, fixed by fixing the way '$' is escaped in the regex.
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BlackBoxSourceHelper should only run late in compilation to allow
transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).
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* Add compiler option (`-p`) to emit individual module protobufs
* Implement multi module combination when reading directory of protobufs
Co-authored-by: Jack Koenig <koenig@sifive.com>
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We treat it as an assertion that the stop will
never be enabled. stop(0) will still be ignored
(but now demoted to a info from a warning).
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* Fix dshl zero-width shift behavior
Add a special case for dshl handling in the ZeroWidths pass. If one
expression is shifted by a second, zero-width expression, just return
the first expression. This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Fix dshl zero-width shift behavior
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Uses virtual method .getBytesBuffered: Iterable[Array[Byte]] to optimize
file emission.
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NoCommonSubexpressionEliminationAnnotation (#2329)
to make it has the same form with NoDCEAnnotation and NoConstantPropagationAnnotation
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This will make it easier for formal verification
libraries to make use of these emitters.
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(#2324)
Both transforms are (most likely) not needed.
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The SMT backend actually needs to run PropagatePresetAnnotations
(as will treadle at some point).
None of the Verilog specific passes were actually required!
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* implement NoCommonSubexpressionElimination to resolve chipsalliance/chisel3#2006
* Update src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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This reverts commit 2630537cf956eea3768c5bd8e57de839f7d3700a.
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Fix an OG bug where Andr, Orr, and Xorr would accept an arbitrary number
of operands. Verilog emission doesn't support this and will silently
drop all operands after the first. E.g., "andr(a, b)" would emit as
"&a". After this commit, "andr(a, b)" will be rejected by checking
passes.
For archaeological purposes, this appears to have been the behavior
dating back to when this was added in d2d3260a.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* rearrange passes to enable optimized firrtl emission
* Support ConstProp on padded arguments to comparisons with literals
* Move shr legalization logic into ConstProp
Continue calling ConstProp of shr in Legalize.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add new util "groupByIntoSeq"
* Restore annotation order when dedupping annotations
* Attribute annotations now deduplicate
* Implement doc string anno dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* deprecate DependencyAPIMigration.
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This will allow chiseltest to save
the hash code to disk for the purpose
of caching simulation binaries.
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This is a bug fix, before this PR, Scala compiler will infer `Nothing`, which makes code below failed to compile:
```
class UserCompiler extends TransformManager(Seq(Dependency(UserPass))) {
override def optionalPrerequisiteOf: Seq[TransformDependency] = Seq(
Dependency[DedupModules]
)
}
```
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* Add transform to deduplicate memory annotations
* Add annotation deduplication to Dedup stage
* ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform
* Verilog emitter now throws exception when memory annotations fail to dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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The pass injects pipe registers immediately after the declaration of the
memory. This can be problematic if the clock for the associated memory
port is defined after the declaration of the memory. For any memory port
clocks that are driven by non-ports, we now inject a wire before the
pipe register declarations to be sure there are no
use-before-declaration issues.
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* Restore parsed MultiInfo structure in firrtl parser
* Change erroneous expected output in InfoSpec test
FileInfo compression sorts the outputted entries alphabetically, but
this test did not reflect that fact
* Fix typo in comment
* Add unit tests for file locator parsing
* Fix syntax issues and typos
* More redundant braces removed
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* smt: include firrtl statement names in SMT and btor2 output
* smt: remove println
* smt: make tests run again and fix stale ones
Apparently `private` classes aren't found by th sbt test runner.
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Add a new option to the FIRRTL compiler, "--start-from = <form>". If
used, this will cause the compiler to assume that the input FIRRTL
circuit is already in the specific form. It will then skip unnecessary
passes given this information.
E.g., if a user requests to run "firrtl -X verilog --start-from low"
then the compiler will only run transforms necessary to get from low
FIRRTL to Verilog. Transforms necessary for ingesting FIRRTL IR will be
run if needed (checks and type/kind/flow resolution).
To implement this, a CurrentFirrtlStateAnnotation is added. Advanced
users can use this directly to tell the FIRRTL compiler exactly what
transforms have already been run, including the ability to ignore checks
or type/kind/flow resolution if they so desire.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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* Add Protocol Buffer emission export
This adds infrastructure and annotations that let a user emit a FIRRTL
circuit as a Protocol Buffer.
Fixes #1696.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* fixup! Add Protocol Buffer emission export
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* make PresetRegAnnotation public
this annotation is useful outside the firrtl compiler:
- to implement a pass that creates registers which
need to be initialized at the beginning of simulation
(e.g., for formal verification)
- to support preset registers in treadle
* add PresetRegAnnotation test and deal with annotation correctly in RemoveReset pass
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Add a compiler/emitter that can target minimal high form. This will
produce output that only has CHIRRTL constructs removed.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Requested by reviewer.
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* ReplaceMemMacros: add target rename test case
* ReplaceMemMacros: rename references to instances
* fix renaming for deduped mems
* use grouped DummyAnnos to preserve order
* Apply suggestions from code review
Co-authored-by: Jack Koenig <koenig@sifive.com>
* run scalafmt
* flatten targets
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen
* Add CLI support for GenVerilogMemBehaviorModelAnno
* Add simple test for GenVerilogMemBehaviorModelAnno
* Fix for review
1. rename case class Port(prefix, `type`) to Port(prefix, portType)
2. fix AnnotatedMemoriesAnnotation collect function.
3. fix bug that ModuleName is not correct.
* Format DumpMemoryAnnotations & ReplSeqMemTests
* Fix for review
1. Inline genDecl, genPortSpec, genSequential, genCombinational
2. Add DefAnnotatedMemory informations in header
3. Change helpText
4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog
* Fix ReadWritePort mask name
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* add more inline renaming test cases
* InlineInstances: fix renaming for local targets
* run scalafmt
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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