diff options
| author | Kevin Laeufer | 2021-05-20 19:17:31 -0700 |
|---|---|---|
| committer | GitHub | 2021-05-21 02:17:31 +0000 |
| commit | abb8b4c90e7218129783372235619be00a215d66 (patch) | |
| tree | 1c1e89d7c46f21fb97df991ba5e45b027f7a4cca /src/main | |
| parent | e0844966cbd2eb44b66c8bf341fa26370e3b4f1c (diff) | |
WiringTransform: cannot run after RemoveWires (#2240)
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/passes/wiring/WiringTransform.scala | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala index 86afe520..d8b8eed9 100644 --- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala +++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala @@ -40,7 +40,9 @@ class WiringTransform extends Transform with DependencyAPIMigration { override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def optionalPrerequisiteOf = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters ++ + // once wire targets are turned into nodes, our logic to wire them up no longer works + Seq(Dependency[firrtl.transforms.RemoveWires]) private val invalidates = Forms.VerilogOptimized.toSet -- Forms.MinimalHighForm override def invalidates(a: Transform): Boolean = invalidates(Dependency.fromTransform(a)) |