diff options
| -rw-r--r-- | src/main/scala/firrtl/passes/wiring/WiringTransform.scala | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala index 86afe520..d8b8eed9 100644 --- a/src/main/scala/firrtl/passes/wiring/WiringTransform.scala +++ b/src/main/scala/firrtl/passes/wiring/WiringTransform.scala @@ -40,7 +40,9 @@ class WiringTransform extends Transform with DependencyAPIMigration { override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def optionalPrerequisiteOf = Forms.MidEmitters + override def optionalPrerequisiteOf = Forms.MidEmitters ++ + // once wire targets are turned into nodes, our logic to wire them up no longer works + Seq(Dependency[firrtl.transforms.RemoveWires]) private val invalidates = Forms.VerilogOptimized.toSet -- Forms.MinimalHighForm override def invalidates(a: Transform): Boolean = invalidates(Dependency.fromTransform(a)) |