Hotfix for Vector Reg Init LegalizeConnects Bug

Add a private pass, LegalizeConnectsOnly, that behaves like
LegalizeConnects, but only pads connects instead of connects and
register inits.  Padding is necessary for ReplSeqMem, but ReplSeqMem
runs before LowerTypes and vector registers can still exist at this
point.  Connects, conversely, are all blown out by ExpandConnects and
can be safely, blindly treated as ground type.

Fixes #2379.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

2 files changed, 21 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/passes/LegalizeConnects.scala b/src/main/scala/firrtl/passes/LegalizeConnects.scala
index 2f29de10..9b60b5f1 100644
--- a/src/main/scala/firrtl/passes/LegalizeConnects.scala
+++ b/src/main/scala/firrtl/passes/LegalizeConnects.scala
@@ -29,3 +29,23 @@ object LegalizeConnects extends Pass {
     c.copy(modules = c.modules.map(_.mapStmt(onStmt)))
   }
 }
+
+/** Ensure that all connects have the same bit-width on the RHS and the LHS.
+  */
+private[firrtl] object LegalizeConnectsOnly extends Pass {
+
+  override def prerequisites = Seq(Dependency(ExpandConnects))
+  override def optionalPrerequisites = Seq.empty
+  override def optionalPrerequisiteOf = Seq.empty
+  override def invalidates(a: Transform) = false
+
+  def onStmt(s: Statement): Statement = s match {
+    case c: Connect =>
+      c.copy(expr = PadWidths.forceWidth(bitWidth(c.loc.tpe).toInt)(c.expr))
+    case other => other.mapStmt(onStmt)
+  }
+
+  def run(c: Circuit): Circuit = {
+    c.copy(modules = c.modules.map(_.mapStmt(onStmt)))
+  }
+}
diff --git a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
index 9acccafa..ccb6f615 100644
--- a/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
+++ b/src/main/scala/firrtl/passes/memlib/ReplaceMemTransform.scala
@@ -152,7 +152,7 @@ class ReplSeqMem extends SeqTransform with HasShellOptions with DependencyAPIMig
 
   val transforms: Seq[Transform] =
     Seq(
-      new SimpleMidTransform(LegalizeConnects),
+      new SimpleMidTransform(LegalizeConnectsOnly),
       new SimpleMidTransform(ToMemIR),
       new SimpleMidTransform(ResolveMaskGranularity),
       new SimpleMidTransform(RenameAnnotatedMemoryPorts),