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2020-08-13Remove LegacyAnnotation and [most] MoultingYaml (#1833)Jack Koenig
* Remove LegacyAnnotation and MoultingYaml It has been deprecated since 1.1 * Remove all uses of ConvertLegacyAnnotations Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-13Cleanup Named Targets (#1311)Schuyler Eldridge
* Add CleanupNamedTargets Transform Adds a new transform, CleanupNamedTargets, that will convert ReferenceTargets to InstanceTargets if any ReferenceTargets are found to be actually pointing at instances. This fixes an issue where a ComponentName pointing at an instance will be converted to a ReferenceTarget. Later on, this ReferenceTarget will not be properly renamed by other transforms, e.g., EliminateTargetPaths. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Update ScalaTests Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-12Combined Uniquify and LowerTypes pass (#1784)Kevin Laeufer
* Utils: add to_dir helper function * firrt.SymbolTable trait for scanning declarations * ir: RefLikeExpression trait to represent SubField, SubIndex, SubAccess and Reference nodes * add new implementation of the LowerTypes pass * replace LowerTypes with NewLowerTypes * remove dependencies on Uniquify * GroupComponentSpec: GroupComponents is run before lower types * NewLowerTypes: address Adam's suggestions * LoweringCompilerSpec: Uniquify was removed and NewLowerTypes * LowerTypesSpec: add newline at the end of file * LowerTypesSpec: port Uniquify tests to combined pass * NewLowerTypes: ensure that internal methods are not visible * NewLowerTypes: extend DependencyAPIMigration * NewLowerTypes: lower ports without looking at the body * LowerTypesSpec: use TransformManager instead of hard coded passes. * NewLowerTypes: names are already assumed to be part of the namespace * LowerTypesSpec: test name clashes between ports and nodes, inst, mem * NewLowerTypes: correctly rename nodes, mems and instances that clash with port names * NewLowerTypes: Iterable[String] instead of Seq[String] for 2.13 * NewLowerTypes: add a fast path for ground types without renaming * LowerTypesSpec: remove trailing commans for 2.11 * LowerTypesSpec: explain why there are two * Uniquify: use loweredName from NewLowerType * replace old LowerTypes pass with NewLowerTypes pass * Uniquify: deprecate pass usage There are some functions that are still used by other passes. * LowerTypes: InstanceKeyGraph now has a private constructor * LowerTypes: remove remaining references to NewLowerTypes * LoweringCompilerSpec: fix transform order to LowerTypes * SymbolTable: add improvements from PR * LoweringCompilerSpec: ignore failing CustomTransform tests
2020-08-12Strip dependencies from BlackBoxSourceHelper (#1840)Schuyler Eldridge
Remove all prerequisites and optionalPrerequisites from BlackBoxSourceHelper. These were false dependencies that were added without me actually looking at what the transform does. BlackBoxSourceHelper is an identity transform that only performs IO side effects based on Chisel-generated annotations. Therefore this transform can literally run anytime it wants without consequence. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-08-11File Serialization of Annotations (#1277)Schuyler Eldridge
* Transform, not run in LegalizeAndReduction test Switch from using FirrtlStage.transform to FirrtlStage.run in one test. The latter is problematic as it doesn't include wrappers or pre/post phases which are how things will work in the future for doing file writing (via HowToSerialize ideas). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Use execute in FIRRTL testing infra (not run) Changes the FirrtlStage method in FIRRTL testing infrastructure from "run" (which does not include Stage-global Phases) to "execute" (which does). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add HowToSerialize Annotation mix-in This adds an Annotation mix-in, HowToSerialize, that allows an annotation to declare how it should be serialized to a file. The mix-in is abstract in a baseFileName and a suffix (used to generate a filename), a howToSerialize method (defining the string contents of the file), and a howToResume method (that defines a replacement for the file-serialized annotation that allows this to be resumed) [^1]. A default implementation for generating a filename (called filename) is defined that will put the baseFileName+suffix file in the target directory. This can be overridden by the annotation if desired. [^1]: When an annotation is serialized to a file, it should be removed from the emitted JSON-serialized annotations. The howToResume method defines a way of adding replacement annotations to the JSON-serialized annotations that tell a downstream tool how to find the serialized file. E.g., if a FIRRTL circuit is written to a file, this could be used to add a FirrtlFileAnnotation defining the location of the new file. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Handle HowToSerialize in WriteOutputAnnotations This extends firrtl.options.phase.WriteOutputAnnotations to serialize HowToSerialize annotations to files. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Test HowToSerialize in WriteOutputAnnotationsSpec This adds tests of the HowToSerialize mix-in inside the WriteOutputAnnotationsSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * [skip chisel tests] Migrate to HowToSerialize This migrates EmittedAnnotations (and its children) to mixin the HowToSerialize trait. This enables this annotations to be automatically written to files via WriteOutputAnnotations Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Deprecated firrtl.stage.phases.WriteEmitted Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Use streams in HowToSerialize This converts the HowToSerialize trait to use a Stream[Char] when defining how an annotation should be serialized. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Switch from Stream[Char] to Stream[Byte] Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Change howToSerialize method to Iterable Change the type of the HowToSerialize.howToSerialize method from a stream to an iterable. Using the latter (the superset of both lazy streams and non-lazy things like String) avoids problems with users having to choose laziness when they already have an eager object. In effect, this makes the API more general. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add Scaladoc to HowToSerialize trait Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Change HowToSerialize to CustomFileEmission Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add default implementation of replacements Add a default implementation of CustomFileEmission.replacements. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Avoid unnecessary 2x monad in CustomFileEmission Change the type of CustomFileEmission.replacements from Option[AnnotationSeq] to AnnotationSeq. The latter has all the properties of the former that I'm trying to express here: (1) can emptiness and (2) monadicity (if the AnnotationSeq is converted to a sequence first). The latter property is exploited in the WriteOutputAnnotations phase to concisely flatMap over the annotations and doing the double-monad is unnecessary. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Restrict CustomFileEmission filename API Change the API of CustomFileEmission to use a final def for the actual filename. The baseFileName is then made a method with an AnnotationSeq parameter to allow the filename to change as a function of other annotations, e.g., by an output circuit annotation. By restricting this API, we have more control over the default behavior of where things are written using the fixed behavior of the filename method---files will always be written using the behavior that StageOptions define. Previously, if users want customized behavior, they would need to duplicate this StageOptions functionality (and likely subtly deviate from the standard behavior and introduce problems with their build). Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add file conflict behavior for CustomFileEmission Set behavior of file conflicts in CustomFileEmission to be the following: No two annotations in the same annotation sequence can serialize to the same file during the WriteOutputAnnotations phase. However, if the output annotation file already exists, it will be overwritten. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Return relative path from getBuildFileName Change FirrtlOptions.getBuildFileName to simply serialize the underlying Java File instead of converting this to its canonical path. This should improve the relocatability of files produced by the CustomFileEmission API. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Normalize paths in StageOptions.getBuildFile Normalize paths inside the getBuildFileName utility of StageOptions. Add a check to prevent a null pointer dereference. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Refer to CustomFIleEmission in deprecation message Co-authored-by: Jack Koenig <koenig@sifive.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Simplify CustomFileEmission toBytes implementation Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Use toBytes, not getBytes, in CustomFileEmission Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-08-11stage: allow a RunFirrtlTransformAnnotation(_:Emitter) annotation to be used ↵Kevin Laeufer
in place of a CompilerAnnotation (#1835)
2020-08-07ExpandWhens: VerificationStatements should be part of the simlist (#1829)Kevin Laeufer
2020-08-06Add deprecations for more firrtl.Compiler methods (#1791)Schuyler Eldridge
Adds missing deprecation warnings to firrtl.Compiler methods: compile and compileAndEmit. This provides a more informative message to the user about how to actually migrate. Without this, the user only has the generic deprecation warning about class Compiler. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-05ir: add UseSerializer mixin trait (#1824)Kevin Laeufer
Using the new trait to overwrite serialize at the leaf classes, we ensure that new, e.g., Expression nodes will not automatically try to call `Serializer.serialize` which would fail by default. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-08-05Deprecate InstanceGraph (#1800)Kevin Laeufer
* InstanceKeyGraph: add staticInstanceCount, getGraph and getChildrenInstanceMap * InstanceKeyGraph: reachableModules, unreachableModules, lowestCommonAncestor and fullHierarchy * Replace usage of InstanceGraph with InstanceKeyGraph Also deprecates all unused methods. * WiringUtils: make new version of sinksToSources package private This will make our live easier next time we need to change it. * CircuitGraph: use InstanceKeyGraph * InstanceKeyGraphSpec: respect maximum line width * InstanceKeyGraph: make constructor private * InstanceKeyGraph: move lowestCommonAncestor function to Wiring * WiringUtils: update deprecation message
2020-08-01Error on ExtModules w/ same defname, diff. ports (#1734)Schuyler Eldridge
* Use signed output in LargeParamExecutionTest Change the Verilog used in LargeParamExecutionTest to match its ExtModule specification. An ExtModule with an SInt port should map to a separate Verilog module with a signed port and this is disjoint from an ExtModule with a UInt port. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Error on ExtModules w/ same defname, diff. ports Adds a high form check to ensure that external modules that have the same defname also have exactly the same ports. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-31Avoid repeated inlining in FlattenRegUpdate (#1727)Jack Koenig
* Avoid repeated inlining in FlattenRegUpdate When-else structure can lead to the same complex mux structure being the default on several branches in register update logic. When these are inlined, it can lead to artifical unreachable branches that show up as coverage holes in coverage of the emitted Verilog. This commit changes the inlining logic to prevent inlining any reference expression that shows up multiple times because this is a common indicator of the problematic case. * Add tests for improved register update logic emission * Improve FlattenRegUpdate comment and add more tests * [skip formal checks] ICache equivalence check verified locally
2020-07-31CircuitGraph: remove fields from public API (#1813)Kevin Laeufer
They are never used outside of the class not even in tests.
2020-07-31[WIP] Implement CircuitGraph and IRLookup to firrtl.analyses (#1603)Jiuyang Liu
* WIP Commit * Add EdgeDataDiGraph with views to amortize graph construction * WIP, got basic structure, need tests to pipeclean * First tests pass. Need more. * Tests pass, more need to be written * More tests pass! Things should work, except for memories * Added clearPrev to fix digraph uses where caching prev breaks * Removed old Component. Documented IRLookup * Added comments. Make prev arg to getEdges * WIP: Refactoring for CircuitGraph * Refactored into CircuitGraph. Can do topological module analysis * Removed old versions * Added support for memories * Added cached test * More stufffff * Added implicit caching of connectivity * Added tests for IRLookup, and others * Many major changes. Replaced CircuitGraph as ConnectionGraph Added CircuitGraph to be top-level user-facing object ConnectionGraph now automatically shortcuts getEdges ConnectionGraph overwrites BFS as PriorityBFS Added leafModule to Target Added lookup by kind to IRLookup Added more tests * Reordered stuff in ConnectionGraph * Made path work with deep hierarchies. Added PML for IllegalClockCrossings * Made pathsInDAG work with current shortcut semantics * Bugfix: check pathless targets when shortcutting paths * Added documentation/licenses * Removed UnnamedToken and related functionality * Added documentation of ConnectionGraph * Added back topo, needed for correct solving of intermediate modules * Bugfix. Cache intermediate clockSources from same BFS with same root, but not BFS with different root * Added literal/invalid clock source, and unknown top for getclocksource * Bugfix for clocks in bundles * Add CompleteTargetSerializer and test * remove ClockFinder, be able to compile. * test is able to compile, but need to fix. * public and abstract DiGraph, remove DiGraphLike. * revert some DiGraph code, ConnectionGraphSpec passed. * CircuitGraphSpec passed. * minimize diff between master * codes clean up * override linearize and revert DiGraph * keep DiGraph unchanged. * make ci happy again. * codes clean up. * bug fix for rebase * remove wir * make scaladoc happy again. * update for review. * add some documentation. * remove tag * wip IRLookup * code clean up and add some doucmentations. * IRLookup cache with ModuleTarget guarded. * make unidoc and 2.13 happy Co-authored-by: Adam Izraelevitz <azidar@gmail.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-07-30ir: use Serializer.serialize where possible (#1809)Kevin Laeufer
* ir: use Serializer.serialize where possible * ir.Serializer: serialize MultiInfo correctly * ir.Serializer: empty body needs to result in a skip statement The firrtl grammar requires at least one statement. * ir.Serializer: correctly serialize fixed point types and literals * Serializer: change Seq -> Iterable in order to be Scala 2.13 compatible
2020-07-29ManipulateNames: use composition instead of extending HashMapKevin Laeufer
2020-07-29[2.13] fix legacy procedure syntaxKevin Laeufer
2020-07-29[2.13] use scala.collection.Seq instead of mutable.SeqKevin Laeufer
2020-07-29PropagatePreset: use partition function to find other annotationsKevin Laeufer
2020-07-29[2.13] EmissionOptionMap now uses a HashMap instead of extending itKevin Laeufer
Extending HashMap is discouraged.
2020-07-29[2.13] replace `= Unit` with `= ()`Kevin Laeufer
2020-07-29Compiler: clarify package of DedupModulesKevin Laeufer
2020-07-29MemConf: build list of tuples and turn it into a map at the endKevin Laeufer
2020-07-29[2.13] convert toSeq and toMap where necessary to compileKevin Laeufer
2020-07-29[2.13] explicitly use a parallel vectorKevin Laeufer
2020-07-29WiringTransform: fix non-determinism (#1799)Kevin Laeufer
* WiringUtils.sinksToSources: make sinkInsts order deterministic * WiringUtils: make owners a LinkedHashMap * Wiring: only make something a Wire if it isn't a port already Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29RemoveWires: improve dependencies and declare ResolveKinds as an ↵Kevin Laeufer
invalidation (#1797) Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-29InferTypes: fix bugs with unknown widths on ports and memories (#1769)Kevin Laeufer
* InferTypesFlowsAndKindsSpec: test the results of InferTypes, ResolveKinds and ResolveFlows * Don't use passes sub-package in tests This changes two test files using the "passes" sub-package to "firrtl.passes". This allows a new "firrtlTests.passes" package to be freely created and used without a name collision. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * ResolveFlows: only depends on types and working ir The types are needed to know the orientation of a bundle field of a SubField node. * InferTypes: fix bugs with unknown widths on ports and memories * LoweringCompileSpec: Uniquify pass moved Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-28Fix incorrect error message (#1795)Andrew Waterman
dshl amount must be < 20 bits, not <= 20 bits. Resolves #1794
2020-07-27Add adapter to make current CHIRRTL mport scoping legalAlbert Magyar
* See #1505 * Inferred mports are implicitly added to scope of their parent mem * This allows current chisel3 emission to work with new scope checks * This may change in a future refactor of CHIRRTL memory ports
2020-07-27Honor block scoping of Conditionally in CheckHighFormAlbert Magyar
* Fixes #1505
2020-07-25Integrate new transforms with firrtl.stage.Forms (#1754)Schuyler Eldridge
Move new transforms, recently added, into existing or new sets of transforms (defined in firrtl.stage.Forms). One transform is a mandatory low FIRRTL optimization: - firrtl.transforms.LegalizeAndReductionsTransform Previously, this was included as a prerequisite of all Verilog emitters (minimum, normal, and SystemVerilog). Two transforms associated with converting and removing the new verification statements are moved into a new set of transforms, AssertsRemoved: - firrtl.transforms.formal.ConvertAsserts - firrtl.transforms.formal.RemoveVerificationStatements Previously, these transforms were directly added as prerequisites to the minimum Verilog and normal Verilog emitter, but not the SystemVerilog emitter. The designation of inputForm=LowForm for legacy, custom transforms is updated to include assertion removal transforms as part of their optionalPrerequisites. This has the effect of continuing to cause inputForm=LowForm transforms to run as late as possible (right before the low FIRRTL, minimum Verilog, Verilog, or SystemVeriog emitter). Tests are updated to reflect the new order in both CustomTransformSpec and LoweringCompilersSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-24Fix sign extension issue in Emitter (#1785)Albert Chen
* add sign-extend const-prop test * Emitter: don't wrap Neg operand in concat
2020-07-23fix reduction op bug ConstantPropagation (#1746)Albert Chen
* add const prop bitwise reduction equivalence test * mask negative literals when propagating reduction * change widths * get rid of unnecessary if * add BigInt mask utility
2020-07-23mask bits when propagating bitwise ops (#1745)Albert Chen
* ConstProp: test bitwise op of signed literals * ConstProp: use bit mask for FoldOr/FoldXor * handle and also * add UIntLiteral.masked helper Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-07-23Update negative literal emission (#1782)Albert Chen
* test const prop of addition of negative literals * Emitter: handle minimum negative values correctly * update expected verilog in AsyncResetSpec
2020-07-20Make InferWidths thread safe (#1775)Schuyler Eldridge
Change the class-global, but private ConstraintSolver object inside InferWidths to instead be constructed on each execute invocation. This prevents issues with thread safety where running the same InferWidths object at the same time would cause the ConstraintSolver to get trampled on. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-18Faster dedup instance graph (#1732)Kevin Laeufer
* dedup: add faster InstanceGraph implementation and use it in dedup The new implementation takes care not to hash the instance types contained in DefInstance nodes. This should make dedup considerably faster. * FastInstanceGraph: cache vertices for faster findInstancesInHierarchy * FastInstanceGraph: remove the parent name field since it isn't actually necessary * FastInstanceGraph -> InstanceKeyGraph * InstanceGraph: describe performance problems. * InstanceKeyGraph: turn moduleMap into a def instead of a val This will make changing implementation details much easier in the future. * InstanceKeyGraph: return childInstances as Seq instead of Map This ensures a deterministic iteration order and it can easily be turned into a Map for O(1) accesses. * InstanceKeyGraph: add tests for public methods * InstanceKeyGraph: group public methods together * InstanceKeyGraphSpec: fix wording of a comment Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-17Propagate source locators to register update always blocks (#1743)Jack Koenig
* [WIP] Propagate source locators to Verilog if-else emission * Add and fix tests for reg update info propagation * Add limited source locator propagation in ConstProp Support propagating source locators on connections or nodes where the right-hand side is simply a reference. This case comes up a lot for registers without a synchronous reset. node _T_1 = x @[MyFile.scala 12:10] node _T_2 = _T_1 z <= x Previousy the source locator would be lost, now the result is: z <= x @[MyFile.scala 12:10] * Address review comments Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-15ir: store FileInfo string in escaped format (#1690)Kevin Laeufer
This should speed up the common case as the compiler never operates on the unescaped string. The new escape function also fixes a bug where ']' was not escaped even though it is the delimiting character for FileInfo. In order to maintain backwards compatibility for the ProtoBuf format, this patch adds escape/unescape calls when going from/to protobuf format. For better performance we should consider changing the protobuf format.
2020-07-14Make TopWiringTransform run before LowerTypes (#1750)Schuyler Eldridge
Add an optionalPrerequisiteOf to TopWiringTransform pointing at LowerTypes. This fixes a bug where top-wired wire bundles with flips could result in the top-wired, flattened bundle having every field with an "output" direction if the TopWiringTransform is moved around in the transform order (see FIRRTL issue #1744). Why did this happen? Fundamentally, this stems from the fact that LowerTypes preserves bundle direction for ports, but destroys it for wires. Specifically, The TopWiringTransform creates ports of the "output" direction that are copies of the underlying type of the component being top-wired. Before LowerTypes, the type of a bundle has direction information via flips. After LowerTypes, the lowered ground type does not have this information. Therefore, all the ports are ground type outputs. Simply ensuring that TopWiringTransform must run before LowerTypes avoids this problem. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-14Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-07-14Fix parsing of info on multi-line registers (#1735)Jack Koenig
For multi-line registers, the parsed source locator is located in a different place in the concrete syntax tree than it is for other Statements. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-10Remove Left Over References to Gender in Code (#1752)Kevin Laeufer
* RemoveAccess: update gender to flow * ExpandWhens: update female to sink * RemoveCHIRRTL: female -> sink, male -> source
2020-07-08dedup: use structural sha256 hash instead of agnostify and serialize (#1731)Kevin Laeufer
* benchmark: add hot.DedupBenchmark * dedup: use structural md5 hash instead of agnostify and serialize * StructuralHash: generate PrimOp LUT * StructuralHash: change MessageDigestHasher to not be a case class * StructuralHash: we want Blocks and EmptyStmt to be ignored * StructuralHash: use SHA-256 instead of MD5 * StructuralHash: clarify extmodule port name agnistification * StructuralHash: hash the name of width vars instead of trying to agnostify This should be in line with the old Dedup behavior. The prior use of n(..) was incorrect since the namespace of these vars is different from the normal module scope namespace. * StructuralHash: address Schuyler's review comments Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-08ir: add faster serializer (#1694)Kevin Laeufer
This Serializer which is implemented external to the IR node definition uses a StringBuilder to achieve about a 1.7x performance improvement when serializing. Eventually, all implementations of the `serialize` methd should be replaced with a call to `Serializer.serialize`. However, for this PR we keep the old code in place in order to allow for easy regression testing with the benchmark JAR like this: > java -cp utils/bin/firrtl-benchmark.jar \ firrtl.benchmark.hot.SerializationBenchmark \ ~/benchmarks/medium.pb 2 5 test Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-07verification: emit mesage as Verilog comment (#1712)Kevin Laeufer
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-01Fix unchecked type in ManipulateNames (#1726)Schuyler Eldridge
Fix a bug where a type check would always yield true. This caused a bug where allow/block-list annotations would be incorrectly applied to all subtypes of ManipulateNames. The tests are updated to check that this now works. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-06-26Enable ConvertAsserts in default Verilog compilerAlbert Magyar
2020-06-26Add ConvertAsserts transform to map asserts to Verilog-friendly nodesAlbert Magyar
* ConvertAsserts maps each assert into a gated print-and-stop * ConvertAsserts is an optional prereq of RemoveVerificationStatements * ConvertAsserts generates Low FIRRTL * Drop print for asserts that have an empty message * Fix scaladoc formatting from review Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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