diff options
| author | Jack Koenig | 2020-07-14 12:24:29 -0700 |
|---|---|---|
| committer | GitHub | 2020-07-14 19:24:29 +0000 |
| commit | 596b766639cff559e52dd51c1b7c0e3f6f58e11d (patch) | |
| tree | 40b6f461c3ead75eb7f0156e4236ae4d206ddc54 /src/main | |
| parent | 0a6fe35205e9f478beef62ac167a084ce90aca63 (diff) | |
Fix parsing of info on multi-line registers (#1735)
For multi-line registers, the parsed source locator is located in a
different place in the concrete syntax tree than it is for other
Statements.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/Visitor.scala | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala index 48a887de..76b5c2cf 100644 --- a/src/main/scala/firrtl/Visitor.scala +++ b/src/main/scala/firrtl/Visitor.scala @@ -304,16 +304,17 @@ class Visitor(infoMode: InfoMode) extends AbstractParseTreeVisitor[FirrtlNode] w case "reg" => val name = ctx.id(0).getText val tpe = visitType(ctx.`type`()) - val (reset, init) = { + val (reset, init, rinfo) = { val rb = ctx.reset_block() if (rb != null) { val sr = rb.simple_reset.simple_reset0() - (visitExp(sr.exp(0)), visitExp(sr.exp(1))) + val innerInfo = if (info == NoInfo) visitInfo(Option(rb.info), ctx) else info + (visitExp(sr.exp(0)), visitExp(sr.exp(1)), innerInfo) } else - (UIntLiteral(0, IntWidth(1)), Reference(name, tpe)) + (UIntLiteral(0, IntWidth(1)), Reference(name, tpe), info) } - DefRegister(info, name, tpe, visitExp(ctx_exp(0)), reset, init) + DefRegister(rinfo, name, tpe, visitExp(ctx_exp(0)), reset, init) case "mem" => visitMem(ctx) case "cmem" => val (tpe, size) = visitCMemType(ctx.`type`()) |