diff options
| author | Albert Chen | 2020-07-24 13:56:49 -0700 |
|---|---|---|
| committer | GitHub | 2020-07-24 20:56:49 +0000 |
| commit | b24b9a0167762b7f7ef1aae3fd6735a3bb1f898e (patch) | |
| tree | 69cc83d07519b5c0ab043823b14eee06c2775811 /src/main | |
| parent | e30c20d10ba47b11e06416e912ed89b6b6ce8e7b (diff) | |
Fix sign extension issue in Emitter (#1785)
* add sign-extend const-prop test
* Emitter: don't wrap Neg operand in concat
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index fdfda3e6..850c8ca1 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -398,7 +398,7 @@ class VerilogEmitter extends SeqTransform with Emitter { error("Verilog emitter does not support SHIFT_RIGHT >= arg width") case Shr if c0 == (bitWidth(a0.tpe)-1) => Seq(a0,"[", bitWidth(a0.tpe) - 1, "]") case Shr => Seq(a0,"[", bitWidth(a0.tpe) - 1, ":", c0, "]") - case Neg => Seq("-{", cast(a0), "}") + case Neg => Seq("-", cast(a0)) case Cvt => a0.tpe match { case (_: UIntType) => Seq("{1'b0,", cast(a0), "}") case (_: SIntType) => Seq(cast(a0)) |