From b24b9a0167762b7f7ef1aae3fd6735a3bb1f898e Mon Sep 17 00:00:00 2001
From: Albert Chen
Date: Fri, 24 Jul 2020 13:56:49 -0700
Subject: Fix sign extension issue in Emitter (#1785)

* add sign-extend const-prop test

* Emitter: don't wrap Neg operand in concat---
 src/main/scala/firrtl/Emitter.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index fdfda3e6..850c8ca1 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -398,7 +398,7 @@ class VerilogEmitter extends SeqTransform with Emitter {
          error("Verilog emitter does not support SHIFT_RIGHT >= arg width")
        case Shr if c0 == (bitWidth(a0.tpe)-1) => Seq(a0,"[", bitWidth(a0.tpe) - 1, "]")
        case Shr => Seq(a0,"[", bitWidth(a0.tpe) - 1, ":", c0, "]")
-       case Neg => Seq("-{", cast(a0), "}")
+       case Neg => Seq("-", cast(a0))
        case Cvt => a0.tpe match {
          case (_: UIntType) => Seq("{1'b0,", cast(a0), "}")
          case (_: SIntType) => Seq(cast(a0))
-- 
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