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AgeCommit message (Expand)Author
2015-08-18Emit random initialization instead of zero initialization for Verilog regazidar
2015-08-17Removed leading zeros from UInt constantsazidar
2015-08-17Fixed bug where equality between expressions was incorrect, leading toazidar
2015-08-17Added tests for shl and mem. Fixed bug in verilog output of mem size.azidar
2015-08-05Added type inference before gender checkazidar
2015-08-05Fixed bug in temp elimination.azidar
2015-08-04Added check for reading from outputs with flipsazidar
2015-08-04Added () around width printersazidar
2015-08-04Added verilog keywords to uniquify themazidar
2015-08-04Fixed reading from instance's input ports. Fixed unique naming bug.azidar
2015-08-03Changed name mangling to use _ as a delin. Fixed bug in checking forazidar
2015-08-03Added concrete syntax for EmptyStmt()azidar
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect indexed...azidar
2015-07-31Fixed (?) resolve genders passazidar
2015-07-31Reading from output ports no longer causes errorsazidar
2015-07-31Fixed inferred type of bits and bitazidar
2015-07-31Fixed compiletime error, whooopsazidar
2015-07-31Allow bit operations on sintsazidar
2015-07-31Added errors for bulk connects where field names match but types/flips don'tazidar
2015-07-30Added module name to error messages.azidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-30Added primitive linking to firrtl-test-mainazidar
2015-07-30Started adding linking supportazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-29Finished supporting Chisel 2.0 Ref ChipAdam Izraelevitz
2015-07-29Add bigint support.Adam Izraelevitz
2015-07-28Integrated bigint. Mostly works, but getting "cast" error for make Test.Adam Izraelevitz
2015-07-22Fixed verilog so it emits non-random inital values. Changed Not to beAdam Izraelevitz
2015-07-21Firrtl generates verilog that compiles, but does not workAdam Izraelevitz
2015-07-21Fixed bug in fix :Pazidar
2015-07-21Fixed removing non-referenced componentsazidar
2015-07-21Made things go faster. Still in progress. Expand when now removesAdam Izraelevitz
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
2015-07-16Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtlazidar
2015-07-16Fixed rename to work with chisel3 stuffazidar
2015-07-14Fixed performance bug in backend. Added renamingazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added te...azidar
2015-07-14Added clock supportazidar
2015-07-14Updated flo backendazidar
2015-07-14Passes riscv-mini testsazidar
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14Partial commitazidar
2015-07-14In progress commitazidar
2015-07-14Fixed bug in lowering, where the indexes to many-connects and accessors weren...azidar
2015-07-13Added tests for clocks. Added remove scope and special chars passes. Added te...azidar
2015-07-10Added clock supportazidar
2015-07-07Updated flo backendazidar
2015-07-07Passes riscv-mini testsazidar
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