Added check for reading from outputs with flips

4 files changed, 12 insertions, 7 deletions

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 1ca84035..c3c29c40 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -32,7 +32,7 @@ public defmethod passes (c:StandardFlo) -> List<Pass> :
       Inline()
       SplitExp()
       ToRealIR()
-      RemoveSpecialChars()
+      ;RemoveSpecialChars()
       CheckHighForm()
       CheckLowForm()
       Flo(with-output(c))
@@ -56,13 +56,14 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       CheckGenders()
       ExpandAccessors()
       LowerToGround()
+      CheckGenders()
       ExpandIndexedConnects()
       ExpandWhens()
       InferWidths()
       Pad()
       SplitExp()
       ToRealIR()
-      RemoveSpecialChars()
+      ;RemoveSpecialChars()
       CheckHighForm()
       CheckLowForm()
       CheckInitialization()
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index edb9928e..bfeb980b 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -725,6 +725,12 @@ public defn check-genders (c:Circuit) -> Circuit :
    defn check-gender (info:FileInfo,genders:HashTable<Symbol,Gender>,e:Expression,desired:Gender) -> False :
       val gender = get-gender(e,genders)
       val kind* = get-kind(e)
+      val flip? = 
+         match(type(e)) :
+            (t:BundleType) : 
+               for f in fields(t) any? : flip(f) == REVERSE
+            (t) : false
+         
       ;println(e)
       ;println(gender)
       ;println(desired)
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index e1f91254..bdc063d4 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -9,10 +9,8 @@ public defmethod info! (x:?) : FileInfo()
 public val vector-expand-delin = `$
 public val bundle-expand-delin = `$
 public val module-expand-delin = `$
-public val scope-delin = `%
-public val temp-delin = `!
-public val sub-delin = `*
-public val inline-delin = `^
+public val scope-delin = `_
+public val inline-delin = `_
 public val delin = `_
 
 public definterface PortDirection
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index a868929b..1ac91658 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -392,7 +392,7 @@ defn remove-scopes (c:Circuit) :
             val i = get?(uses,n,0)
             uses[n] = i + 1
             env[length(env) - 1][n] = i
-            symbol-join([n `% i])
+            symbol-join([n scope-delin i])
          else : n
       defn build-s (s:Stmt) :
          match(s) :