diff options
| -rw-r--r-- | src/main/stanza/compilers.stanza | 5 | ||||
| -rw-r--r-- | src/main/stanza/errors.stanza | 6 | ||||
| -rw-r--r-- | src/main/stanza/firrtl-ir.stanza | 6 | ||||
| -rw-r--r-- | src/main/stanza/passes.stanza | 2 | ||||
| -rw-r--r-- | test/passes/infer-types/primops.fir | 4 |
5 files changed, 14 insertions, 9 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 1ca84035..c3c29c40 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -32,7 +32,7 @@ public defmethod passes (c:StandardFlo) -> List<Pass> : Inline() SplitExp() ToRealIR() - RemoveSpecialChars() + ;RemoveSpecialChars() CheckHighForm() CheckLowForm() Flo(with-output(c)) @@ -56,13 +56,14 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : CheckGenders() ExpandAccessors() LowerToGround() + CheckGenders() ExpandIndexedConnects() ExpandWhens() InferWidths() Pad() SplitExp() ToRealIR() - RemoveSpecialChars() + ;RemoveSpecialChars() CheckHighForm() CheckLowForm() CheckInitialization() diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index edb9928e..bfeb980b 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -725,6 +725,12 @@ public defn check-genders (c:Circuit) -> Circuit : defn check-gender (info:FileInfo,genders:HashTable<Symbol,Gender>,e:Expression,desired:Gender) -> False : val gender = get-gender(e,genders) val kind* = get-kind(e) + val flip? = + match(type(e)) : + (t:BundleType) : + for f in fields(t) any? : flip(f) == REVERSE + (t) : false + ;println(e) ;println(gender) ;println(desired) diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index e1f91254..bdc063d4 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -9,10 +9,8 @@ public defmethod info! (x:?) : FileInfo() public val vector-expand-delin = `$ public val bundle-expand-delin = `$ public val module-expand-delin = `$ -public val scope-delin = `% -public val temp-delin = `! -public val sub-delin = `* -public val inline-delin = `^ +public val scope-delin = `_ +public val inline-delin = `_ public val delin = `_ public definterface PortDirection diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index a868929b..1ac91658 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -392,7 +392,7 @@ defn remove-scopes (c:Circuit) : val i = get?(uses,n,0) uses[n] = i + 1 env[length(env) - 1][n] = i - symbol-join([n `% i]) + symbol-join([n scope-delin i]) else : n defn build-s (s:Stmt) : match(s) : diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index 89c06e7e..45c88a43 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -150,10 +150,10 @@ circuit top : node wnot = not(a) ;CHECK: node wnot = not(a@<t:UInt>)@<t:UInt> node unot = not(c) ;CHECK: node unot = not(c@<t:SInt>)@<t:SInt> - node wand = and(a, b) ;CHECK: node wand = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node wand_ = and(a, b) ;CHECK: node wand_ = and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> node uand = and(c, d) ;CHECK: node uand = and(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - node wor = or(a, b) ;CHECK: node wor = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node wor_ = or(a, b) ;CHECK: node wor_ = or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> node uor = or(c, d) ;CHECK: node uor = or(c@<t:SInt>, d@<t:SInt>)@<t:SInt> node wxor = xor(a, b) ;CHECK: node wxor = xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt> |