| Age | Commit message (Expand) | Author |
|---|
| 2016-01-28 | Fixed matching on types for and, or, and xor | azidar |
| 2016-01-28 | Fixed bug and updated test for changing mod to rem | azidar |
| 2016-01-28 | Changed mod to rem | azidar |
| 2016-01-28 | Updated with new primops. Removed addw,subw,quo,rem,bit. Added head,tail,asCl... | azidar |
| 2016-01-28 | Fixed readwriter syntax, and all printed mstats to use => instead of a colon | azidar |
| 2016-01-28 | Changed register syntax for optional reset and init values | azidar |
| 2016-01-27 | WIP Moving Scala FIRRTL to match spec 0.2.0. Not everything is implemented (n... | jackkoenig |
| 2016-01-27 | Reworked readwriter types | azidar |
| 2016-01-27 | Fixed additional tests and inferring rdwr ports in chirrtl | jackkoenig |
| 2016-01-27 | Merge branch 'scala-new-mem' | jackkoenig |
| 2016-01-25 | Fixed bug where poisons were not being declared | azidar |
| 2016-01-25 | Added verilog rename pass | azidar |
| 2016-01-25 | Added isinvalid and validif | azidar |
| 2016-01-25 | Removed println in expand when | azidar |
| 2016-01-25 | Fixed width inference bug for muxes | azidar |
| 2016-01-25 | Removed random println | azidar |
| 2016-01-25 | Fixed support for muxes and nodes with passive aggregate types | azidar |
| 2016-01-25 | Changed first generated name to use _0 postfix | azidar |
| 2016-01-24 | Made CInfer robust to high firrtl errors | azidar |
| 2016-01-24 | Added muxing on passive aggregate types | azidar |
| 2016-01-24 | Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-mem | azidar |
| 2016-01-24 | Removed hashing as it made refchip slower to compile | azidar |
| 2016-01-24 | Added DefMemory to CInfer Types | azidar |
| 2016-01-23 | Fix Verilog syntax errors for print/stop | Andrew Waterman |
| 2016-01-23 | Removed buggy optimization of dshr and dshl | azidar |
| 2016-01-23 | Moved inst declarations after other declarations | azidar |
| 2016-01-23 | Fixed commas for instances in verilog | azidar |
| 2016-01-23 | Added more semicolons | azidar |
| 2016-01-23 | Added semicolon after assigns in verilog | azidar |
| 2016-01-23 | off by one error when emitting ports in verilog | azidar |
| 2016-01-23 | Fixed combinational read verilog backend | azidar |
| 2016-01-23 | Removed more prints ;) | azidar |
| 2016-01-23 | Removed print statements | azidar |
| 2016-01-23 | Fixed bug where the write mask wasn't being generated correctly | azidar |
| 2016-01-23 | Removed debugging printlns | azidar |
| 2016-01-23 | Added inference to mports | azidar |
| 2016-01-23 | Added prefix checker, now compliant with firrtl spec | azidar |
| 2016-01-23 | Changed chirrtl to not require known mask values | azidar |
| 2016-01-20 | WIP, need to update chirrtl with new mask syntax | azidar |
| 2016-01-17 | Forgot to add the changes | azidar |
| 2016-01-17 | Removed temporary files | azidar |
| 2016-01-17 | BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests | azidar |
| 2016-01-16 | Add warning that -p unused | ducky |
| 2016-01-16 | Clean up old logging remnants | ducky |
| 2016-01-16 | Import a logging library so we don't reinvent the wheel and have implicits fl... | ducky |
| 2016-01-16 | Refactor passes system | ducky |
| 2016-01-16 | Added notes for Richard to work on | azidar |
| 2016-01-16 | Standard Verilog doesn't use Resolve(), but lists out the resolution passes i... | azidar |
| 2016-01-16 | Fixed bug in lowering memories that had aggregate data types | azidar |
| 2016-01-16 | Fixed bug in check-init that allows it to check on non-lowered things | azidar |
