| Age | Commit message (Expand) | Author |
|---|
| 2016-02-09 | Added license to FIRRTL files | azidar |
| 2016-01-28 | Changed mod to rem | azidar |
| 2016-01-16 | WIP | azidar |
| 2016-01-16 | WIP need to correctly output readwrite ports | azidar |
| 2016-01-16 | Printf no longer adds a new line | azidar |
| 2016-01-16 | shift right does not cast input as signed | azidar |
| 2016-01-16 | Extraction inputs are no longer cast | azidar |
| 2016-01-16 | Moved integer declaration inside module to be verilog (not system-verilog) co... | Adam Izraelevitz |
| 2016-01-16 | Stop now emits correct verilog to stop simulation, required passing a string ... | azidar |
| 2016-01-16 | Fixed bug in printf and stop to correctly print to STDERR | azidar |
| 2016-01-16 | Finished adding clocks to Stop and Print | azidar |
| 2015-10-07 | Added Printf and Stop to firrtl. #23 #24. | azidar |
| 2015-10-06 | Merge pull request #45 from ucb-bar/change-mem-type | Adam Izraelevitz |
| 2015-10-01 | Changed DefMemory to be a non-vector type with a size member. Necessary for A... | azidar |
| 2015-09-30 | Moved To-Real-Ir earlier, so CheckWidth could happen before PadWidth | azidar |
| 2015-08-26 | Fixed bug where subfields weren't entirely removed | azidar |
| 2015-08-25 | Fix Verilog backend for mixed signed-unsigned ops | Andrew Waterman |
| 2015-08-25 | Removed IntWidth, now only use LongWidth. Now do width inference for Constant... | azidar |
| 2015-08-20 | Added Poison node. Includes tests. #26. | azidar |
| 2015-08-18 | Fixed verilog emission from rand to random | azidar |
| 2015-08-18 | Fixed so its length is greater than what it connects to. Changed shr to be e... | azidar |
| 2015-08-18 | Emit random initialization instead of zero initialization for Verilog reg | azidar |
| 2015-08-17 | Added tests for shl and mem. Fixed bug in verilog output of mem size. | azidar |
| 2015-08-04 | Added verilog keywords to uniquify them | azidar |
| 2015-07-30 | Added module name to error messages. | azidar |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-29 | Add bigint support. | Adam Izraelevitz |
| 2015-07-28 | Integrated bigint. Mostly works, but getting "cast" error for make Test. | Adam Izraelevitz |
| 2015-07-22 | Fixed verilog so it emits non-random inital values. Changed Not to be | Adam Izraelevitz |
| 2015-07-21 | Firrtl generates verilog that compiles, but does not work | Adam Izraelevitz |
| 2015-07-17 | Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog! | Adam Izraelevitz |
| 2015-07-16 | Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtl | azidar |
| 2015-07-14 | Fixed performance bug in backend. Added renaming | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Passes riscv-mini tests | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-14 | Partial commit | azidar |
| 2015-07-14 | In progress commit | azidar |
| 2015-07-13 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-10 | Added clock support | azidar |
| 2015-07-07 | Passes riscv-mini tests | azidar |
| 2015-07-06 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-06 | Partial commit | azidar |
| 2015-07-06 | In progress commit | azidar |
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar |
| 2015-06-02 | Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ... | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
