sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-08-15	Remove stanza (#231)	Adam Izraelevitz
	* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-02-09	Added license to FIRRTL files	azidar

2016-01-28	Fixed matching on types for and, or, and xor	azidar

2016-01-28	Changed mod to rem	azidar

2016-01-28	Updated with new primops. Removed addw,subw,quo,rem,bit. Added ↵	azidar
	head,tail,asClock.
2016-01-24	Added muxing on passive aggregate types	azidar

2016-01-17	BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests	azidar

2016-01-16	Fixed a bunch of tests, and minor bugs	azidar

2016-01-16	WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵	azidar
	roadblock in assigning clocked ports
2016-01-16	WIP	azidar

2016-01-16	Width of multiply is sum of input widths	azidar

2015-08-25	Removed IntWidth, now only use LongWidth. Now do width inference for ↵	azidar
	Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt
2015-07-31	Fixed inferred type of bits and bit	azidar

2015-07-31	Fixed compiletime error, whooops	azidar

2015-07-31	Allow bit operations on sints	azidar

2015-07-30	Added eqv for bitwise equality, and change eq to be arithmetic equality	azidar

2015-06-02	merge + fix trim to use correct bits operands	jackbackrack

2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar

2015-05-21	fix pad/trim pass and fix bug in bits-select width inference	jackbackrack

2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be ↵	azidar
	flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-05-04	Added a few more error checks. Not tested yet. Fixed bug in pad type inference	azidar

2015-05-04	Fixed change where type of mux-ss was incorrect	azidar

2015-05-02	Added a infrastructure for check passes, and wrote a few	azidar

2015-05-01	Fixed bug where the enable was looked at for lowering MUX.	azidar

2015-04-29	Added dshl and dshr	azidar

2015-04-24	Fixed switch statement	azidar

2015-04-24	NEG now propogates input args plus one	azidar

2015-04-24	Updated TODO. Added backwards with prop for as and bits	azidar

2015-04-24	Incorrectly propagated width constraint for non-muxes. This is only true for ↵	azidar
	muxes
2015-04-24	Fixed width inference bug where later constraints on the output width were ↵	azidar
	not propogating to the input widths, for primops
2015-04-22	Switched to stricter primop width constraints. Implemented Pad. Added some ↵	azidar
	missing primops
2015-04-17	Removed excessive debug print statements, added default call to firrtl to ↵	azidar
	generate flo
2015-04-17	Fixed bug in primop lowering during type inference. Added reduce ↵	azidar
	instructions and renamed concat -> cat, equal -> eq, and added neq and neg