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path: root/src/main/stanza/ir-parser.stanza
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2016-08-15Remove stanza (#231)Adam Izraelevitz
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-02-09Added license to FIRRTL filesazidar
2016-02-09More bug fixesazidar
2016-01-28Changed mod to remazidar
2016-01-28Updated with new primops. Removed addw,subw,quo,rem,bit. Added ↵azidar
head,tail,asClock.
2016-01-28Fixed readwriter syntax, and all printed mstats to use => instead of a colonazidar
2016-01-28Changed register syntax for optional reset and init valuesazidar
2016-01-25Added isinvalid and validifazidar
2016-01-24Added muxing on passive aggregate typesazidar
2016-01-23Added inference to mportsazidar
2016-01-23Changed chirrtl to not require known mask valuesazidar
2016-01-20WIP, need to update chirrtl with new mask syntaxazidar
2016-01-16Finished first cut at new firrtl - time for testing! Chirrtl requires masks ↵azidar
to be specified with write and rdwr mports
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16WIP Almost there, need to generate enable connectionsazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵azidar
roadblock in assigning clocked ports
2016-01-16WIP, hit semantic bug in WSubAccessazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2016-01-16WIP. Compiles and almost done with verilog backend. Need to think about ↵azidar
emitting ports (and the assignments to them)
2016-01-16WIP. Compiles, need to testazidar
2016-01-16WIPazidar
2016-01-16Finished adding clocks to Stop and Printazidar
2015-10-07Added Printf and Stop to firrtl. #23 #24.azidar
2015-10-01Changed DefMemory to be a non-vector type with a size member. Necessary for ↵azidar
ASIC backend.
2015-08-26Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37.azidar
2015-08-25Removed IntWidth, now only use LongWidth. Now do width inference for ↵azidar
Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt
2015-08-20Added Poison node. Includes tests. #26.azidar
2015-08-20Added rsh to BigInt library. Const Prop now works on rsh's on constants. #19.azidar
2015-08-19Switched to new bigint libraryazidar
2015-08-19Check Neg UInt in the parserazidar
2015-08-03Added concrete syntax for EmptyStmt()azidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-29Finished supporting Chisel 2.0 Ref ChipAdam Izraelevitz
2015-07-29Add bigint support.Adam Izraelevitz
2015-07-28Integrated bigint. Mostly works, but getting "cast" error for make Test.Adam Izraelevitz
2015-07-21Made things go faster. Still in progress. Expand when now removesAdam Izraelevitz
non-referenced declarations that are not instances, but it doesn't work right now.
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
Had to separate initialization check pass Need to write dead code elimination pass Added LongWidth to support dshl that are huge
2015-07-14Added clock supportazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14In progress commitazidar
2015-07-02Fixed stanza, optimize works, added a time printoutazidar
2015-07-02Hopefully fixed stanza so it can correctly compile itselfazidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. ↵azidar
Added Long support so UInt(LARGENUMBER) works
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ↵azidar
smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ↵azidar
instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be ↵azidar
flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ↵azidar
Should show up with check passes
2015-04-29Added dshl and dshrazidar
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