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AgeCommit message (Expand)Author
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
2020-01-07Remove unnecessary casts in Constant PropagationJack Koenig
2020-01-06Verilog emitter transform InlineNots (#1270)John Ingalls
2020-01-06Remove incorrect --firrtl-source option (#1266)Schuyler Eldridge
2020-01-06Make EmittedAnnotation Unserializable (#1288)Schuyler Eldridge
2019-12-30Minor code cleansup in InferResetsJack Koenig
2019-12-30Respect last connect semantics in InferResetsJack Koenig
2019-12-18Improve Scaladoc (#1284)Schuyler Eldridge
2019-12-18Fix incorrect ScalaDoc link (#1282)Schuyler Eldridge
2019-12-16{Firrtl, Circuit}Option should be Unserializable (#1278)Schuyler Eldridge
2019-12-11Make the member 'logger' added by the trait LazyLogging protected. (#1271)Jim Lawson
2019-12-06Move --no-dedup from stage-global to firrtl-local (#1265)Schuyler Eldridge
2019-12-03Logger tweaks (#1190)edwardcwang
2019-11-29Remove scala-logging fully in favor of our own loggerJack Koenig
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
2019-11-18Make updated type info available in VerilogMemDelays (#1243)Albert Magyar
2019-11-14Use getName instead of getSimpleNameSchuyler Eldridge
2019-11-07Add check for multiple sources for same wiring pin (#1191)Jack Koenig
2019-11-05Move CheckResets after CheckCombLoops (#1224)Jack Koenig
2019-11-04Merge branch 'master' into serialization-utilsJack Koenig
2019-11-04Ignore extmodule instances in Flatten (#1218)Albert Magyar
2019-10-31Guard initial blocks in emitted Verilog with `ifndef SYNTHESISJack Koenig
2019-10-29Remove an unneeded castDavid Biancolin
2019-10-29Some cleanupDavid Biancolin
2019-10-29Update src/main/scala/firrtl/annotations/JsonProtocol.scalaDavid Biancolin
2019-10-29Check that all annotations provide the typeHintDavid Biancolin
2019-10-29Try implementing recursive typeHint look upDavid Biancolin
2019-10-29Change findInstancesInHierarchy to return implicit top instanceAlbert Magyar
2019-10-25Only emit the DeserilizationTypeHintsAnno when neededDavid Biancolin
2019-10-24Enhance CheckCombLoops errors with connection infoAlbert Magyar
2019-10-24Add EdgeData trait to mix in to graphsAlbert Magyar
2019-10-24Supply a trait to allow user annotations to provide SERDES type hintsDavid Biancolin
2019-10-22Emit Verilog "else if" in register updatesSchuyler Eldridge
2019-10-21Fix write-first mem enable handling in VerilogMemDelaysAlbert Magyar
2019-10-18Upstream intervals (#870)Adam Izraelevitz
2019-10-08Make TopWiringTransform idempotentSchuyler Eldridge
2019-10-07Absorb some instance analysis into InstanceGraph, use safer boxed Strings (#1...Albert Magyar
2019-10-03Add Block factory from argument list of Statements (#1197)Albert Magyar
2019-10-01Restore ResolveGenders to its status as a Pass (#1192)Jack Koenig
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
2019-09-30Add read-under-write checks for memory emissionAlbert Magyar
2019-09-30Improve read-under-write parameter supportAlbert Magyar
2019-09-19Faster inline renaming (#1184)Albert Chen
2019-09-17Speed up InlineInstances (#1182)Jack Koenig
2019-09-16Deprecate Gender and add implicit Flow conversionSchuyler Eldridge
2019-09-16Rename gender to flowSchuyler Eldridge
2019-09-12Add space, s/Github/GitHub/ in DontTouchException (#1177)Schuyler Eldridge
2019-09-12update inline transform and testcasesAbert Chen
2019-09-06Refactor: remove redundancy code (#1166)Leway Colin
2019-09-05Filter out more filename extensions for blackbox source headers (#1134)Albert Magyar
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