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(#2423)
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* split big Emitter to submodules.
* fix all deprecated warning.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* - modify firrtlEquivalenceTest to use yosys equiv_simple/equiv_induct instead of miter
- add RemoveValidIf pass to MinimumLowFirrtlOptimization
* add EquivalenceTest to FirrtlSpec.scala, make classes in IntegrationSpec.scala abstract
* change types of inputForm/outputForm to CircuitForm
* change EquivalenceTest message
* remove ICache equivalence tests
* fix rebase errors
* Add Ops scalatests to LEC suite
* Only run compiler-path-comparison LEC tests on Ops design
* Fixup issues with merge
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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* adding init macros
* fix missing tick
* adding more documentation; fixing up emitter tests
* adding initial-guarding macro test
* prefixing macros with FIRRTL
* cleanup
* typo fix
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This includes the built-in functions in BackendCompilationUtilities
which are a public API
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Fixes a threading bug in where lazy reading of file
caused a problem for multithreaded access to the that was read.
Changes all uses of io.Source to use new API
getText
getLines
getTextResource
getLinesResouce
Make style to only import FileUtils and not its methods
So code is more explicit as e.g. FileUtils.getText()
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* Allow name of blackbox resource .f file to change from static value
* Restore fileListName as a deprecated def per Jack's feedback
* Support both local and absolute paths for .f resource files
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* Add sbt-scalafix
* Add scalafix guide to README
* Remove Unused Import
* Remove deprecated procedure syntax
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This adds FirrtlStage, a reimplementation of the original FIRRTL
Driver as a Stage. This updates the original firrtl.options package to
implement FirrtlStage (namely, TransformLike is added) along with
FirrtlMain. Finally, the original FIRRTL Driver is converted to a
compatibility wrapper around FirrtlStage.
For background, Stage and Phase form the basis of the Chisel/FIRRTL
Hardware Compiler Framework (HCF). A Phase is a class that performs a
mathematical transformation on an AnnotationSeq (in effect, a
generalization of a FIRRTL transform). Curtly, a Stage is a Phase that
also provides a user interface for generating annotations. By their
construction, Phases are designed to be composed sequentially into a
transformation pipeline.
This modifies the existing options package (which provides
Stage/Phase) to build out a type hierarchy around Stage/Phase. This
adds TransformLike[A] which implements a mathematical transformation
over some type A. Additionally, and as an interface between different
TransformLikes, this adds Translator[A, B] which extends
TransformLike[A], but does an internal transformation over type B.
This is used to interface Phases with the existing FIRRTL compiler.
This adds a runTransform method to Phase that, like
Transform.runTransform, will automatically detect deleted Annotations
and generate DeletedAnnotations.
The new FirrtlStage, a reimplementation of FIRRTL's Driver, is added
as a Stage composed of the following Phases:
1. AddDefaults - add default annotations
2. AddImplicitEmitter - adds an implicit emitter derived from the
compiler
3. Checks - sanity check the AnnotationSeq
4. AddCircuit - convert FIRRTL input files/sources to circuits
5. AddImplicitOutputFile - add a default output file
6. Compiler - run the FIRRTL compiler
7. WriteEmitted - write any emitted modules/circuits to files
The Driver is converted to a compatibility layer that replicates old
Driver behavior. This is implemented by first using new toAnnotation
methods for CommonOptions and FirrtlExecutionOptions that enable
AnnotationSeq generation. Second, the generated AnnotationSeq is
preprocessed and sent to FirrtlStage. The resulting Phase order is
then:
1. AddImplicitAnnotationFile - adds a default annotation file
2. AddImplicitFirrtlFile - adds a default FIRRTL file using top name
3. AddImplicitOutputFile - adds an output file from top name
4. AddImplicitEmitter - adds a default emitter derived from a
compiler and any split modules command line option
5. FirrtlStage - the aforementioned new FirrtlStage
Finally, the output AnnotationSeq is then viewed as a
FirrtlExecutionResult. This compatibility layer enables uninterrupted
usage of old Driver infrastructure, e.g., FirrtlExecutionOptions and
CommonOptions can still be mutated directly and used to run the
Driver.
This results in differing behavior between the new FirrtlStage and the
old Driver, specifically:
- FirrtlStage makes a clear delineation between a "compiler" and an
"emitter". These are defined using separate options. A compiler is
"-X/--compiler", while an emitter is one of "-E/--emit-circuit" or
"-e/--emit-modules".
- Related to the above, the "-fsm/--split-modules" has been removed
from the FirrtlStage. This option is confusing once an implicit
emitter is removed. It is also unclear how this should be handled
once the user can specify multiple emitters, e.g., which emitter
should "--split-modules" apply to?
- WriteOutputAnnotations will, by default, not write
DeletedAnnotations to the output file.
- The old top name ("-tn/--top-name") option has been removed from
FirrtlStage. This option is really a means to communicate what
input and output files are as opposed to anything associated with
the circuit name. This option is preserved for the Driver
compatibility layer.
Additionally, this changes existing transform scheduling to work for
emitters (which subclass Transform). Previously, one emitter was
explicitly scheduled at the end of all transforms for a given
compiler. Additional emitters could be added, but they would be
scheduled as transforms. This fixes this to rely on transform
scheduling for all emitters. In slightly more detail:
1. The explicit emitter is removed from Compiler.compile
2. An explicit emitter is added to Compiler.compileAndEmit
3. Compiler.mergeTransforms will schedule emitters as late as
possible, i.e., all emitters will occur after transforms that
output their input form.
4. All AddImplicitEmitter phases (DriverCompatibility and normal)
will add RunFirrtlTransformAnnotations to add implicit emitters
The FIRRTL fat jar utilities are changed to point at FirrtlStage and not
at the Driver. This has backwards incompatibility issues for users
that are using the utilities directly, e.g., Rocket Chip.
The Logger has been updated with methods for setting options based on
an AnnotationSeq. This migrates the Logger to use AnnotationSeq as
input parameters, e.g., for makeScope. Old-style methods are left in
place and deprecated. However, the Logger is not itself a Stage.
The options of Logger Annotations are included in the base Shell and
Stage is updated to wrap its Phases in a Logger scope.
Additionally, this changes any code that does option parsing to always
prepend an annotation as opposed to appending an annotation. This is
faster, but standardizing on this has implications for dealing with
the parallel compilation annotation ordering.
A Shell will now put the initial annotations first (in the order the
user specified) and then place all annotations generating from parsing
after that. This adds a test case to verify this behavior.
Discovered custom transforms (via `RunFirrtlTransformAnnotation`s) are
discovered by the compiler phase in a user-specified order, but are
stored in reverse order to more efficiently prepend (as opposed to
append) to a list. This now reverses the transform order before
execution to preserve backwards compatibility of custom transform
ordering.
The Compiler phase also generates one deleted annotation for each
`RunFirrtlTransformAnnotation`. These are also reversed.
Miscellaneous small changes:
- Split main method of Stage into StageMain class
- Only mix in HasScoptOptions into Annotation companion objects (h/t
@jackkoenig)
- Store Compiler in CompilerAnnotation
- CompilerNameAnnotation -> CompilerAnnotation
- Make Emitter abstract in outputSuffix (move out of FirrtlOptions)
- Add DriverCompatibility.AddImplicitOutputFile that will add an
output file annotation based on the presence of a
TopNameAnnotation. This is important for compatibility with the
old Driver.
- Cleanup Scaladoc
- Refactor CircuitOption to be abstract in "toCircuit" that converts
the option to a FirrtlCircuitAnnotation. This allows more of the
conversion steps to be moved out of AddCircuit and into the actual
annotation.
- Add WriteDeletedAnnotation to module WriteOutputAnnotations
- A method for accessing a FirrtlExecutionResultView is exposed in
FIRRTL's DriverCompatibilityLayer
- Using "--top-name/-tn" or "--split-modules/-fsm" with FirrtlStage
generates an error indicating that this option is no longer
supported
- Using FirrtlStage without at least one emitter will generate a
warning
- Use vals for emitter in Compiler subclasses (these are used to
build RunFirrtlTransformAnnotations and the object should be
stable for comparisons)
- Fixes to tests that use LowTransformSpec instead of
MiddleTransformSpec. (SimpleTransformSpec is dumb and won't
schedule transforms correctly. If you rely on an emitter, you need
to use the right transform spec to test your transform if you're
relying on an emitter.)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This fixes issue #988
I tried one alternative to this fix: record the time to do a *no rename* run (`depth = 0`) and check that the time to do the *deep rename* (`depth = 500`) was a reasonable multiple of the *no rename* test. Unfortunately, the discrepancies were all over the map, sometime as much three orders of magnitude difference.
I decided the current fix was the simplest - don't enforce timing checks if we're doing coverage testing, although determining the latter is brittle.
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(#883)
* Filter resource file names to avoid including the same file multiple times.
Addresses issue #882.
* Use a Set instead of a Map to filter Verilog files.
* Use canonical paths for file name comparison and unify name generation.
Provide a common method for copying resources to a directory to ensure the same resource ends up with the same name if it's copied by multiple clients.
* Reduce confusion - another absolute -> canonical switch.
Use the canonical path on the verilator command line for the filter additional Verilog sources.
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* add FoldADD to const prop, add yosys miter tests
* add option for verilog compiler without optimizations
* rename FoldLogicalOp to FoldCommutativeOp
* add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation
* add constant propagation for Tail DoPrims
* add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim
* add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass
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Add optional argument to verilogToCpp to suppress VCD
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Create sources once per module, not once per instance
Clean up writing the file list
Don't prepend file list with '-v's (non-standard and not all verilog)
Change file list file name (not all verilog)
Use ListSets for determinism
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When calling verilator in a subdirectory like ./test_run_dir/...
verilator will read the verilog file from the current working directory
if there is a file there with the right name. This fix specifies
the specific path of the verilog file intended.
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* fixed up impementation of deleteDirectoryHierarchy
Added a few more tests
* Round 2 of moving verilog to target dir
Only create .f file if some files have been moved
Some small style fixes in Driver
Restored lost functionality to add -f argument in verilogToCpp
Fixed loadAnnotations to add targetDir regardless of annotations arriving from file or through options
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Will place tests in ./test_run_dir/ instead of /tmp/
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* Move BackendCompilationUtilities into a util package for use by chisel3.
Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ...
* Push util down into firrtl so as not to conflict with scala.util.
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