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Moved from RemoveValidIf
Also Make RemoveValidIf.getGroundZero public and support Fixed
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Improve constant propagation of connections to references
[skip formal checks]
LEC fails on this PR because this PR actually changes the circuit. The
change is that it constant propagates some additional registers. This is
really just extending #621 to work on more registers that it was
supposed to be propagating anyway.
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* Added grouping pass
* Added InfoMagnet and infomappers
* Changed return type of execute to allow final CircuitState inspection
* Updated dedup. Now is name-agnostic
* Added GroupAndDedup transform
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- Old Annotation renamed to deprecated LegacyAnnotation
- Annotation is now a trait that can be extended
- New JsonProtocol for Annotation [de]serialization
- Replace AnnotationMap with AnnotationSeq
- Deprecate Transform.getMyAnnotations
- Update Transforms
- Turn on deprecation warnings
- Remove deprecated Driver.compile
- Make AnnotationTests abstract with Legacy and Json subclasses
- Add functionality to convert LegacyAnnotations of built-in annos
This will give a noisy warning and is more of a best effort than a
robust solution.
Fixes #475 Closes #609
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but not Emitter. (#717)
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* Catch exceptions and convert to internal error.
We need to update the displayed message to incorporate a line number and text to be used for the issue.
* Cleanup exception handling/throwing.
Re-throw expected (or uncorrectable exceptions).
Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain.
Update tests to conform to FreeSpec protocol.
* Minor cleanup
Admit we've updated some deprecated ScalaTest methods.
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Two instances of the same module could collide in counting the number of
instances of each Module. This could lead to constants being propagated
on inputs when it is incorrect to do so.
Fixes #734
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This transform replaces all wires with nodes in a legal, flow-forward
order
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Move pad to object ConstantPropagation so other transforms can use it
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instantiated multiple times (#634)
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* initial implementation of InlineDeepTransformation
* rewrote transformation to not have any side effects in terms on inlining that was not annotated to be inlined
* minor rewrites
* renamed transformations to Flatten
* fixes according to review
* added more comments and fixed formating/style
* fixed spacing, minor style fixes
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Fixes issue in https://github.com/freechipsproject/rocket-chip/pull/848
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Names that do not start with '_' are "better" than those that do
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Constant Propagation will not optimize across components marked
dontTouch
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Resolves #600
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We walked the whole set of vertices for every dont touch
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#504 (#551)
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Fixes #589
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Performs DCE by constructing a global dependency graph starting with top-level
outputs, external module ports, and simulation constructs as circuit sinks.
External modules can optionally be eligible for DCE via the
OptimizableExtModuleAnnotation.
Dead code is eliminated across module boundaries. Wires, ports, registers, and
memories are all eligible for removal. Components marked with a
DontTouchAnnotation will be treated as a circuit sink and thus anything that
drives such a marked component will NOT be removed.
This transform preserves deduplication. All instances of a given DefModule are
treated as the same individual module. Thus, while certain instances may have
dead code due to the circumstances of their instantiation in their parent
module, they will still not be removed. To remove such modules, use the
NoDedupAnnotation to prevent deduplication.
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Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
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This fixes an issue I was having with my ClockListAnnotations being duplicated.
h/t @azidar
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* fixed up impementation of deleteDirectoryHierarchy
Added a few more tests
* Round 2 of moving verilog to target dir
Only create .f file if some files have been moved
Some small style fixes in Driver
Restored lost functionality to add -f argument in verilogToCpp
Fixed loadAnnotations to add targetDir regardless of annotations arriving from file or through options
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* First pass at implementing a annotation based mechanism to move black box verilator files into the target directory
* A little bit of style cleanup
* A little bit of style cleanup
* Fix the driver, wasn't appending targetDir properly
Add some docs
* test had wrong value now that targetdir is added to annnos
* Now saves a list of all black box verilog files moved into target directory.
Then creates a file black_box_verilog_files.f that contains this list with -v prepended to each line
* Made black box source helper be low to low form
Added it to the verilog compiler transforms
Added a test to make sure it got there
* targetDir annotation is targeted to a CircuitName("All")
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FileInfo is merged
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Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel
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getMyAnnotations now returns Seq[Annotation]
Changed test to check number of annotations is the same
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