aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/transforms
diff options
context:
space:
mode:
authorJack Koenig2018-03-28 10:48:54 -0700
committerGitHub2018-03-28 10:48:54 -0700
commitfd8feb55cfa55e2c270d11c1a6ae60ba1950be59 (patch)
tree82d90510de252da6e3b7587b735fa80744f4b8ef /src/main/scala/firrtl/transforms
parentcf0d971beda33a1802c384bd8d5eebb150d9d578 (diff)
Replace unconnected registers with 0 in Constant Propagation (#776)
Moved from RemoveValidIf Also Make RemoveValidIf.getGroundZero public and support Fixed
Diffstat (limited to 'src/main/scala/firrtl/transforms')
-rw-r--r--src/main/scala/firrtl/transforms/ConstantPropagation.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
index 8217a9bd..2def130c 100644
--- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala
+++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
@@ -378,6 +378,8 @@ class ConstantPropagation extends Transform {
nodeMap(lname) = constPropExpression(nodeMap, instMap, constSubOutputs)(pad(fval, ltpe))
case Mux(_, tval: Literal, fval: WRef, _) if weq(lref, fval) =>
nodeMap(lname) = constPropExpression(nodeMap, instMap, constSubOutputs)(pad(tval, ltpe))
+ case WRef(`lname`, _,_,_) => // If a register is connected to itself, propagate zero
+ nodeMap(lname) = passes.RemoveValidIf.getGroundZero(ltpe)
case _ =>
}
// Mark instance inputs connected to a constant