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path: root/src/main/scala/firrtl/transforms
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2019-04-25Add ShellOption, DeletedWrapperSchuyler Eldridge
Abstracts away option writing such that users no longer have to understand scopt semantics. This adds a ShellOption class and a HasShellOptions trait for something which provides one or more ShellOptions. This refactors the FIRRTL codebase to use this style of option specification. Adds and uses DeletedWrapper to automatically generate DeletedAnnotations. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-03-29Faster reg constprop (#1067)Albert Magyar
* Improve memoization for register const prop
2019-03-26DCE printf and stop statements with constant-0 enablesAndrew Waterman
This gets rid of about 10% of the generated Verilog in the rocket-chip default config.
2019-02-27Add --nodedup option to facilitate FIRRTL to verilog regression testing. (#1035)Jim Lawson
* Add --nodedup option to facilitate FIRRTL to verilog regression testing. * Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.
2019-02-25Fix almost all Scaladoc warningsSchuyler Eldridge
This fixes all Scaladoc warnings except for those trying to link to Java. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-21Don't let the main module become deduped out of existence. (#1023)Jim Lawson
2019-02-21Prevent Flatten from stripping all annotations (#1024)Schuyler Eldridge
2019-02-14Asynchronous Reset (#1011)Jack Koenig
Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
2019-02-05Do Shr constant propagation in LegalizeSchuyler Eldridge
This uses the foldShiftRight method of the ConstantPropagation Transform when legalizing Shr PrimOps. This has the effect of removing literals with bit extracts from the MinimumVerilogCompiler. This makes the formerly private foldShiftRight method of a public method of the ConstantPropagation companion object. Tests in the MimimumVerilogCompilerSpec are updated to check that Shr is handled as intended. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-05Missed constprop opportunity (#1009)Andrew Waterman
* Enhance constant propagation across registers * Add more elaborate test case for register const prop
2019-01-21Merge branch 'master' into top-wiring-aggregatesDavid Biancolin
2019-01-13Suppress unchecked warning in Constant PropagationJack Koenig
2019-01-13Constant Propagate dshl and dshr with constant amountsJack Koenig
Fixes #990 h/t @pentin-as and @abejgonzalez
2019-01-13Keep constant propagating expressions until done optimizingJack Koenig
2019-01-04Fix GroupComponents to work with unused componentsJack Koenig
Previously, components that did not affect the output would cause exceptions because they were missing from the label2group Map. This commit treats them as "reachable" by the ports so they are included in the default "ungrouped" group.
2019-01-02Make GroupComponents run ResolveKindsJack Koenig
This fixes an issue where expressions created by GroupComponents would be improperly lowered because they were not marked as references to instance ports.
2018-12-21Enhance CheckCombLoops to support annotated ExtModule paths (#962)Albert Magyar
2018-12-19Add IdentityTransformSchuyler Eldridge
This adds an identity transform that applies an identity function to some CircuitState, i.e., it just returns the original CircuitState. This is useful for transform generators that may, for edge cases, generate an empty transform sequence. Other classes (e.g., Compiler) have explicit or implicit requirements that a transform sequence is non-empty. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-12-13[Top Wiring] Expand top wiring to work on aggregatesDavid Biancolin
2018-12-06Fix bug in dedup where lots of annotations could prevent dedup (#958)Jack Koenig
Iterating on a HashSet could cause identical modules (including annotations) to not dedup
2018-11-29Replace Mappers with Foreachers in several passes (#954)Albert Magyar
2018-11-16Memoize type of instance refs in RemoveKeywordCollisions (#942)Jack Koenig
Huge performance improvement when you have lots of ports for a given module. Also split up some long implicit argument lines.
2018-11-15Combine cats (#851)Albert Chen
- Add firrtl.transforms.CombineCats - Use CombineCats in LowFirrtlOptimization - Modify Verilog emitter to allow for nested Cat DoPrims - Modify firrtlEquivalenceTest to write input FIRRTL string to test directory
2018-11-07Make CheckCombLoops a RegisteredTransformSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-11-07Make DeadCodeElimination a RegisteredTransformSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-31Use Vector instead of List for bulk renaming in RenameMapJack Koenig
2018-10-31Don't include verilog header files in "FileList" for VCS/Verilator. (#918)Jim Lawson
When constructing the black box helper file list (firrtl_black_box_resource_files.f), filter out Verilog header files (*.vh) - Fixes #917
2018-10-30Instance Annotations (#926)Adam Izraelevitz
Formerly #865 Major Code Changes/Features Added: Added Target trait as replacement for Named Added TargetToken as token in building Target Added GenericTarget as a catch-all Target Added CircuitTarget, ModuleTarget, ReferenceTarget, and InstanceTarget Added ResolvePaths annotation Added EliminateTargetPaths (and helper class DuplicationHelper) Updated Dedup to work with instance annotations Updated RenameMap to work with instance annotations DCE & ConstantProp extend ResolveAnnotationPaths
2018-10-27Revert "Instance Annotations (#865)" (#925)Adam Izraelevitz
This reverts commit 7e2f787e125227dc389d5cf1d09717748ecfed2e.
2018-10-24Instance Annotations (#865)Adam Izraelevitz
Added Target, which now supports Instance Annotations. See #865 for details.
2018-10-24Better error message on missing BlackBox resourceSchuyler Eldridge
This wraps interactions with a BlackBox resource file such that a FileNotFoundException are wrapped in a BlackBoxNotFoundException and rethrown. This provides a better, verbose error message to the user and avoids a FileNotFoundException showing up as an internal FIRRTL error. This adds tests that the expected exception is thrown for both BlackBoxResourceAnno and BlackBoxResourceAnno. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-12Refactor VerilogRename -> RemoveKeywordCollisionsSchuyler Eldridge
This moves VerilogRename out of Passes.scala and genericizes it as the new Transform KemoveKeywordCollisions. This new Transform will remove keywords for arbitrary sets of reserved keyword. This adds VerilogRename back as a class instead of an object. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-01add BlackBoxPathAnno (#903)albertchen-sifive
2018-09-26Another TopWiring Bug Fix (Multi-Level Annotations) (#889)alonamid
When different levels of the circuit were annotated, the TopWiring signals of the lower levels would "run-over" the TopWiring signals of the higher levels
2018-09-13Do not remove ExtMods with no ports by default (#888)albertchen-sifive
2018-09-07Bug Fixes in TopWiring (#885)alonamid
* bug fixes in TopWiring
2018-08-29Filter resource file names to avoid including the same file multiple times. ↵Jim Lawson
(#883) * Filter resource file names to avoid including the same file multiple times. Addresses issue #882. * Use a Set instead of a Map to filter Verilog files. * Use canonical paths for file name comparison and unify name generation. Provide a common method for copying resources to a directory to ensure the same resource ends up with the same name if it's copied by multiple clients. * Reduce confusion - another absolute -> canonical switch. Use the canonical path on the verilator command line for the filter additional Verilog sources.
2018-08-24Update DontTouchAnnotation not found error message (#864)Jack Koenig
2018-08-07Make RemoveWires properly include registers in dependency graphJack Koenig
Fixes a bug where registers could be instantiated after nodes that referred to them Also add WRef.apply utility for nodes
2018-07-20Constant prop add (#849)albertchen-sifive
* add FoldADD to const prop, add yosys miter tests * add option for verilog compiler without optimizations * rename FoldLogicalOp to FoldCommutativeOp * add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation * add constant propagation for Tail DoPrims * add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim * add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass
2018-07-10Combinational Dependency Annotation (#809)Adam Izraelevitz
2018-06-28Make CheckCombLoops find combinational nodes with self-edges (#837)Albert Magyar
2018-06-13Resolve register clock dependencies in RemoveWires (#823)Schuyler Eldridge
Candidate fix for #749 This adds DefRegister netlist ordering to RemoveWires Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-06-11Use attach to connect analogs when grouping (#805)Colin Schmidt
2018-06-06ConstProp attached wires if there is also a port (#818)Jack Koenig
This enables the pattern of attaching "through" a wire to give better Verilog that also works in Verilator Use WrappedExpression when combining attaches in ExpandWhens to ensure no duplication of references in resulting, combined attaches
2018-05-29Fix pad (#817)Jack Koenig
* Make VerilogEmitter properly handle pad of width <= width of arg * Constant prop pads with pad amount <= width of arg
2018-05-15Replace truncating add and sub with addw/subw (#800)Jack Koenig
Replaces old VerilogWrap which didn't work with split expressions and was actually buggy anyway. This functionality reduces unnecessary intermediates in emitted Verilog.
2018-05-11TopWiring Transform (#798)alonamid
* top wiring transform * fixup comments * TopWiring cosmetics * move prefix into TopWiringAnnotation * remove test function from transform file * add ChildrenMap to InstanceGraph API * use namespaces * remove wiringUtils from TopWiring pass * enable multiple output functions * TopWiring cosmetics, tests and lowform
2018-05-09Bugfix: ports of a temporary name would break const-prop (#806)Adam Izraelevitz
2018-05-02Deprecate old WiringUtils methods/classes (#801)Schuyler Eldridge
The following are deprecated in favor of DiGraph/InstanceGraph: - firrtl.passes.wiring.Lineage - firrtl.passes.wiring.WiringUtils.ChildrenMap - firrtl.passes.wiring.WiringUtils.getChildrenMap - firrtl.passes.wiring.WiringUtils.getLineage Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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