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Scala FIRRTL Compiler for chiselX
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RemoveReset.scala
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Author
2022-04-21
Fix optimization of register with reset but invalid connection (#2520)
Jack Koenig
2022-01-06
Add FileInfo to asyncResetAlwaysBlocks (#2451)
sinofp
2021-08-02
add emitter for optimized low firrtl (#2304)
Kevin Laeufer
2021-06-15
make PresetRegAnnotation public (#2254)
Kevin Laeufer
2020-09-16
Change to Apache 2.0 License (#1901)
Chick Markley
2020-08-14
All of src/ formatted with scalafmt
chick
2020-07-17
Propagate source locators to register update always blocks (#1743)
Jack Koenig
2020-05-18
Canonicalize init of regs with zero as reset in RemoveReset (#1627)
Albert Magyar
2020-04-22
s/dependents/optionalPrerequisiteOf/
Schuyler Eldridge
2020-04-22
Mixin DependencyAPIMigration to all Transforms
Schuyler Eldridge
2020-03-11
Migrate to DependencyAPI
Schuyler Eldridge
2019-08-07
Improve RemoveReset handling of invalid inits
Schuyler Eldridge
2019-02-14
Asynchronous Reset (#1011)
Jack Koenig
2017-06-27
Add RemoveReset transform to replace register reset with a Mux
Jack Koenig