All of src/ formatted with scalafmt

1 files changed, 3 insertions, 4 deletions

diff --git a/src/main/scala/firrtl/transforms/RemoveReset.scala b/src/main/scala/firrtl/transforms/RemoveReset.scala
index 6b3a9d07..8736e21b 100644
--- a/src/main/scala/firrtl/transforms/RemoveReset.scala
+++ b/src/main/scala/firrtl/transforms/RemoveReset.scala
@@ -18,8 +18,7 @@ import scala.collection.{immutable, mutable}
 object RemoveReset extends Transform with DependencyAPIMigration {
 
   override def prerequisites = firrtl.stage.Forms.MidForm ++
-    Seq( Dependency(passes.LowerTypes),
-         Dependency(passes.Legalize) )
+    Seq(Dependency(passes.LowerTypes), Dependency(passes.Legalize))
 
   override def optionalPrerequisites = Seq.empty
 
@@ -58,7 +57,7 @@ object RemoveReset extends Transform with DependencyAPIMigration {
           reg.copy(reset = Utils.zero, init = WRef(reg))
         case reg @ DefRegister(_, rname, _, _, Utils.zero, _) =>
           reg.copy(init = WRef(reg)) // canonicalize
-        case reg @ DefRegister(info , rname, _, _, reset, init) if reset.tpe != AsyncResetType =>
+        case reg @ DefRegister(info, rname, _, _, reset, init) if reset.tpe != AsyncResetType =>
           // Add register reset to map
           resets(rname) = Reset(reset, init, info)
           reg.copy(reset = Utils.zero, init = WRef(reg))
@@ -68,7 +67,7 @@ object RemoveReset extends Transform with DependencyAPIMigration {
           // Use reg source locator for mux enable and true value since that's where they're defined
           val infox = MultiInfo(reset.info, reset.info, info)
           Connect(infox, ref, Mux(reset.cond, reset.value, expr, muxType))
-        case other => other map onStmt
+        case other => other.map(onStmt)
       }
     }
     m.map(onStmt)