sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2016-10-23	Fix bitmask (#346)	Angie Wang
2016-10-17	Reorganized memory blackboxing (#336)	Adam Izraelevitz
2016-09-25	Spec features added: AnalogType and Attach (#295)	Adam Izraelevitz
2016-09-23	use .head instead of (0)	chick
2016-09-21	swap functions in MemPortUtils and MemTransformUtils properly for further ref...	Donggyu Kim
2016-09-13	Fix a lurking width-inference bug; improve adjacent style (#298)	Andrew Waterman
2016-09-13	use BoolType for UIntType(IntWidth(1))	Donggyu Kim
2016-09-13	use case object for Kind	Donggyu Kim
2016-09-13	type aliases	Donggyu Kim
2016-09-13	remove Utils.{width_BANG, long_BANG}	Donggyu Kim
2016-09-13	MemPortUtils: return correct memory types	Donggyu Kim
2016-09-13	clean up MemUtils	Donggyu Kim
2016-09-12	Change bitWidth to support ClockType	jackkoenig
2016-09-06	Address style feedback and add tests for getConnectOrigin utility	Angie
2016-09-06	Support optionally filling write mask to data width via transform input confi...	Angie
2016-09-06	Changed wmask to convert from VecType to UInt	Angie
2016-09-06	Corrected counting for VectorTypes in MemUtils	Angie
2016-09-06	Minor utility changes.	Angie
2016-08-18	Add MemUtils to aid in interfacing with alternate memory implementations (#244)	Albert Magyar