sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley

2020-08-14	All of src/ formatted with scalafmt	chick

2020-07-29	[2.13] convert toSeq and toMap where necessary to compile	Kevin Laeufer

2019-07-08	Remove some warnings (#1118)	Leway Colin

2018-02-07	Fix EulerTour for circuits with one module (#736)	Schuyler Eldridge
	A circuit with a single module would fail to properly compute BV RMQs due to a divide by zero bug. This changes the computation of the number of blocks an Euler Tour is broken up into to be, at minimum, one. This also changes one of the test cases ("wire with source and sink in the same module") to exercise this. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-01-15	WiringTransform Refactor (#648)	Schuyler Eldridge
	Massive refactoring to WiringTransform with the use of a new EulerTour class to speed things up via fast least common ancestor (LCA) queries. Changes include (but are not limited to): * Use lowest common ancestor when wiring * Add EulerTour class with naive and Berkman-Vishkin RMQ * Adds LCA method for Instance Graph * Enables "Two Sources" using "Top" wiring test as this is now valid * Remove TopAnnotation from WiringTransform * Represent WiringTransform sink as `Seq[Named]` * Remove WiringUtils.countInstances, fix imports * Support sources under sinks in WiringTransform * Enable internal module wiring * Support Wiring of Aggregates h/t @edcote fixes #728 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Reviewed-by: Jack Koenig<jack.koenig3@gmail.com>