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path: root/src/main/scala/firrtl/backends/verilog
AgeCommit message (Expand)Author
2022-03-02Fold VerilogModulusCleanup into LegalizeVerilog (#2485)Jack Koenig
2022-01-27Fix faulty MemorySynthInit behavior (#2468)John's Brew
2022-01-06Add FileInfo to asyncResetAlwaysBlocks (#2451)sinofp
2021-11-19Disable random init (#2396)Jiuyang Liu
2021-10-28typo: correct Error Info (#2398)SingularityKChen
2021-08-02add emitter for optimized low firrtl (#2304)Kevin Laeufer
2021-07-29Dedup attribute annos (#2297)Jared Barocsi
2021-07-14Fix memory annotation deduplication (#2286)Jared Barocsi
2021-04-19Don't use declaration-assigns for wires representing mem ports (#2189)Albert Magyar
2021-04-05Allow direct emission of sync-read memories to VerilogAlbert Magyar
2021-04-01Add memory initialization options for synthesis (#2166)Carlos Eduardo
2021-03-16Fix issue where inlined cvt could cause crash (#2124)Jack Koenig
2021-03-09Fix the readmem statements in nested block (#2109)Carlos Eduardo
2021-03-09Create annotation to allow inline readmem in Verilog (#2107)Carlos Eduardo
2021-02-25Emit space after 'if' for all Verilog conditional synchronous assignments (#2...Albert Magyar
2020-11-10Refactor emiter (#1879)Jiuyang Liu
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