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path: root/src/main/scala/firrtl/backends
AgeCommit message (Expand)Author
2022-08-03smt: make SMTExprMap object public (#2534)Kevin Laeufer
2022-03-02Fold VerilogModulusCleanup into LegalizeVerilog (#2485)Jack Koenig
2022-01-27Fix faulty MemorySynthInit behavior (#2468)John's Brew
2022-01-17[smt] correct comparison for out-of-bounds memory access check (#2463)Kevin Laeufer
2022-01-06Add FileInfo to asyncResetAlwaysBlocks (#2451)sinofp
2021-12-21Remove some warnings (#2448)Jack Koenig
2021-12-21smt: deal correctly with negative SInt literals (#2447)Kevin Laeufer
2021-12-17smt: correctly serialize array index on read (#2446)Kevin Laeufer
2021-12-17Deprecate all mutable methods on RenameMap (#2444)Jack Koenig
2021-11-19Disable random init (#2396)Jiuyang Liu
2021-11-10smt: fix handling of div primitive in formal backend (#2409)Kevin Laeufer
2021-10-28typo: correct Error Info (#2398)SingularityKChen
2021-09-29Add RTLIL Backend. (#2331)Nicolas Machado
2021-09-13Bump Scala to 2.12.14 and 2.13.6 (#2356)Jack Koenig
2021-09-08smt: make SMT + TransitionSystem lib public (#2350)Kevin Laeufer
2021-09-08smt: refactor SMT expression library (#2347)Kevin Laeufer
2021-09-08Multi protobuf module emission and consumption (#2344)Jared Barocsi
2021-08-30[smt] treat stop with non-zero ret like an assertion (#2338)Kevin Laeufer
2021-08-10[smt] make SMTLib + Btor2 emitters public objects (#2326)Kevin Laeufer
2021-08-10[smt] PropagatePresetAnnotations is now a real prereq (#2325)Kevin Laeufer
2021-08-02add emitter for optimized low firrtl (#2304)Kevin Laeufer
2021-07-29Dedup attribute annos (#2297)Jared Barocsi
2021-07-14Fix memory annotation deduplication (#2286)Jared Barocsi
2021-06-17smt: include firrtl statement names in SMT and btor2 output (#2270)Kevin Laeufer
2021-06-17Add Protocol Buffer emission (#2271)Schuyler Eldridge
2021-06-14Add -X mhigh compiler for minimal high form (#2268)Schuyler Eldridge
2021-04-19Don't use declaration-assigns for wires representing mem ports (#2189)Albert Magyar
2021-04-11smt: use existing bitWidth API (#2175)edwardcwang
2021-04-05Allow direct emission of sync-read memories to VerilogAlbert Magyar
2021-04-01Add memory initialization options for synthesis (#2166)Carlos Eduardo
2021-03-16Fix issue where inlined cvt could cause crash (#2124)Jack Koenig
2021-03-09Fix the readmem statements in nested block (#2109)Carlos Eduardo
2021-03-09Create annotation to allow inline readmem in Verilog (#2107)Carlos Eduardo
2021-03-09SMT Backend: model Invalid and Division by Zero with DefRandom nodes (#2104)Kevin Laeufer
2021-03-08SMT: memory port inout fields cannot be used as RHS expressions (#2105)Kevin Laeufer
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
2021-02-25Emit space after 'if' for all Verilog conditional synchronous assignments (#2...Albert Magyar
2021-01-20Cleanup some warnings (#2032)Jack Koenig
2021-01-19Restore scalafmt CI check (#2047)Jack Koenig
2021-01-19smt: run DeadCodeElimination after PropagatePresetAnnotations (#2036)Kevin Laeufer
2020-12-02smt: add support for uninterpreted ext modules (#1994)Kevin Laeufer
2020-11-11smt: add support for write-first memories (#1948)Kevin Laeufer
2020-11-10Fix SMT Memory Bug (#1942)Kevin Laeufer
2020-11-10Refactor emiter (#1879)Jiuyang Liu
2020-11-09smt: ensure that all signals have a unique name (#1943)Kevin Laeufer
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-26smt: ignore clock signals when converting to transition system (#1866)Kevin Laeufer
2020-08-14All of src/ formatted with scalafmtchick
2020-08-15experimental SMTLib and btor2 emitter (#1826)Kevin Laeufer
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