diff options
| author | Jared Barocsi | 2021-07-29 16:31:08 -0700 |
|---|---|---|
| committer | GitHub | 2021-07-29 16:31:08 -0700 |
| commit | 04210ee30acd437bccfe694ddd895e5f450ba01f (patch) | |
| tree | 18212689f16299da9b3df210b92f6a2353c60e9b /src/main/scala/firrtl/backends | |
| parent | 2630537cf956eea3768c5bd8e57de839f7d3700a (diff) | |
Dedup attribute annos (#2297)
* Add new util "groupByIntoSeq"
* Restore annotation order when dedupping annotations
* Attribute annotations now deduplicate
* Implement doc string anno dedup
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'src/main/scala/firrtl/backends')
| -rw-r--r-- | src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala index 8b20d365..4f62f27e 100644 --- a/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala +++ b/src/main/scala/firrtl/backends/verilog/VerilogEmitter.scala @@ -8,6 +8,7 @@ import firrtl.Utils._ import firrtl.WrappedExpression._ import firrtl.traversals.Foreachers._ import firrtl.annotations.{ + Annotation, CircuitTarget, MemoryInitAnnotation, MemoryLoadFileType, @@ -509,14 +510,14 @@ class VerilogEmitter extends SeqTransform with Emitter { case m: SingleTargetAnnotation[ReferenceTarget] @unchecked with EmissionOption => m } - // Check for non-local memory annotations (error if found) - emissionAnnos.foreach { - case a: MemoryInitAnnotation => { - if (!a.target.isLocal) + annotations.foreach { + case a: Annotation if a.dedup.nonEmpty => + val (_, _, target) = a.dedup.get + if (!target.isLocal) { throw new FirrtlUserException( - "At least one memory annotation did not deduplicate: got non-local annotation $a from [[DedupAnnotationsTransform]]" + "At least one dedupable annotation did not deduplicate: got non-local annotation $a from [[DedupAnnotationsTransform]]" ) - } + } case _ => } |
