sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2021-12-21	Remove some warnings (#2448)	Jack Koenig
	* Fix unreachable code warning by changing match order Simulation Statements did not previously extend IsDeclaration, but now they do so their match blocks need to be above IsDeclaration. * Handle MemoryNoInit case in RtlilEmitter * Remove use of deprecated logToFile * Fix uses of LegalizeClocksTransform Replaced all uses of LegalizeClocksTransform with LegalizeClocksAndAsyncResetsTransform. * Remove use of CircuitForm in ZeroWidth
2021-11-19	Disable random init (#2396)	Jiuyang Liu
	* Add option to disable random mem/reg init Co-authored-by: Jiuyang Liu <liu@jiuyang.me> * fix for code review. Co-authored-by: SharzyL <me@sharzy.in>
2021-10-28	typo: correct Error Info (#2398)	SingularityKChen
	+ correct the Error Info of "At least one dedupable annotation..."
2021-09-29	Add RTLIL Backend. (#2331)	Nicolas Machado
	* Added RTLIL Backend. * Add test for Rtlil Backend, fix per-module file emission, scalafmt, and apply bugfixes for inconsistencies found during testing. * Fix build on scala 2.13 * Add additional equivalence test, make some bugfixes and perf opts to the emitter. * Final changes as requested by Kevin, code cleanup, add support for formal cells.