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2021-06-25Correct a typo in src/main/scala/firrtl/WIR.scala (#2283)Felix Yan
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
With this PR the smt backend now supports memories with more than two write ports and the conservative memory modelling can be selectively turned off with a new annotation.
2021-02-17Allow Side Effecting Statement to have Names (#2057)Kevin Laeufer
* firrtl: add optional statement labels for stop, printf, assert, assume and cover * test: parsing of statement labels * ir: ensure that name is properly retained * SymbolTable: add support for labled statements * test: parsing statement labels * test: lower types name collisions with named statements * ignore empty names * Inline: deal with named and unnamed statements * RemoveWires: treat stop, printf and verification statements as "others" * test: fix InlineInstance tests * DeadCodeEliminations: statements are now als declarations * CheckHighForm: ensure that statement names are not used as references * CheckSpec: throw error if statement name collides * add pass to automatically add missing statement names * check: make sure that two statements cannot have the same name * stmtLabel -> stmtName * scalafmt * add statement names to spec * spec: meta data -> metadata * EnsureStatementNames: explain naming algorithm * remove returns * better namespace use * ir: add CanBeReferenced trait * ir: add newline as jack requested
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-14All of src/ formatted with scalafmtchick
2020-08-05ir: add UseSerializer mixin trait (#1824)Kevin Laeufer
Using the new trait to overwrite serialize at the leaf classes, we ensure that new, e.g., Expression nodes will not automatically try to call `Serializer.serialize` which would fail by default. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-30ir: use Serializer.serialize where possible (#1809)Kevin Laeufer
* ir: use Serializer.serialize where possible * ir.Serializer: serialize MultiInfo correctly * ir.Serializer: empty body needs to result in a skip statement The firrtl grammar requires at least one statement. * ir.Serializer: correctly serialize fixed point types and literals * Serializer: change Seq -> Iterable in order to be Scala 2.13 compatible
2020-07-29[2.13] replace `= Unit` with `= ()`Kevin Laeufer
2020-07-17Propagate source locators to register update always blocks (#1743)Jack Koenig
* [WIP] Propagate source locators to Verilog if-else emission * Add and fix tests for reg update info propagation * Add limited source locator propagation in ConstProp Support propagating source locators on connections or nodes where the right-hand side is simply a reference. This case comes up a lot for registers without a synchronous reset. node _T_1 = x @[MyFile.scala 12:10] node _T_2 = _T_1 z <= x Previousy the source locator would be lost, now the result is: z <= x @[MyFile.scala 12:10] * Address review comments Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-26[API change] Absorb repetitive WIR nodes into IRAlbert Magyar
* Absorb WRef into Reference * Absorb WSubField into SubField * Absorb WSubIndex into SubIndex * Absorb WSubAccess into SubAccess * Absorb WDefInstance into DefInstance ------------------------- API CHANGE SEVERITY -------------------------- This is projected to not break source-level compatibility with any known user code. However, it will break *binary* compatibility with all existing user FIRRTL passes, as is generally allowed with major releases of FIRRTL. --------------------------- DESCRIPTION -------------------------------- Previously, there were several nodes in WIR.scala that had a one-to-one correspondance with existing nodes in the standard firrtl.ir hierarchy. These nodes would have a case class resembling the corresponding standard IR node, but with the addition of one or more "analysis" fields. Since these fields (such as kind) represent helpful info that can be invalidated or set to Unknown (e.g. UnknownKind for Kind), it does not cause any issues to simply include these fields on any in-memory representation of FIRRTL IR. Although other systems for tracking FIRRTL analyses have evolved over time, the ubiquity of pattern-matching on these fields has lead most core and custom transforms to be written against WIR, rather than IR. This PR unifies the IRs by adding the fields that would be in an "augmented" WIR node directly into the corresponding IR node; i.e., the "type" and "kind" fields from WRef are added directly to the definition of the Reference case class, while these "repetitive" WIR case classes are removed entirely. -------------------- SOURCE-COMPATIBILITY ADAPTERS --------------------- Several object methods are added to WIR.scala to maintain source-compatiblity for passes that used WIR. These objects define factory methods and unapply methods, so passes that relied on implicit case class factories or pattern matching for the removed WIR types will remain perfectly source-compatible. However, these do not guarantee compatibility at the binary level. The types of the removed WIR case classes are also added as type aliases to the top-level firrtl package, which allows code that relies on explicit constructor calls or reflection to retain source-compatibility. Finally, additional explicit factory methods are added to the companion objects of the newly-augmented IR case classes, which allows user code to avoid having to specify any of the new analysis fields. Existing code that created non-WIR IR nodes will be able to continue using the previous factory signatures, which will cause all omitted analysis fields to be set to Unknown. ---------------------- UNMITIGATED API CHANGES ------------------------- While passes that used WIR will be source-compatible with this change, there is one significant change that affects any pass currently using non-WIR IR: the signatures of pattern-matching cases for Reference, SubField, SubIndex, SubAccess, and DefInstance must change to accommodate the extra fields. This cannot be worked at the API level due to restrictions on unapply overloading, but it could theoretically be solved with macros or other static rewriting. However, only four core transforms (RemoveProto, ToWorkingIR, Dedup, and RemoveChirrtl) use non-WIR IR, and it is expected that no user code currently relies on it, so the expected migration strategy is simply to change the small fraction of code relying on these nodes.
2020-04-06* Remove deprecated 'Gender' methods/aliasesAlbert Magyar
2019-10-18Upstream intervals (#870)Adam Izraelevitz
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-09-30Improve read-under-write parameter supportAlbert Magyar
* Make the read-under-write (RUW) parameter typesafe * Add RUW support to the FIRRTL proto and CHIRRTL grammar
2019-09-16Deprecate Gender and add implicit Flow conversionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-16Rename gender to flowSchuyler Eldridge
The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-13Infer reset (#1068)Jack Koenig
* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1> * Enhance async reset initial value literal check to support aggregates
2019-05-04Use UnknownKind instead misrepresented NodeKind (#1076)Leway Colin
2019-04-22Change Memory Depth to a BigInt (#1075)Jack Koenig
2019-02-14Asynchronous Reset (#1011)Jack Koenig
Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
2019-02-04Correct Kind info from #1010 (#1012)Albert Magyar
2019-02-01Mem helpers (#1010)Albert Magyar
* Add memory WRef factory for completeness * Refactor DefAnnotatedMemory construction for clarity
2019-01-23Improve Shl codegen; eliminate Shlw WIR node (#994)Andrew Waterman
* Improve Shl codegen; eliminate Shlw WIR node If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's no need for Verilog-specific padding in the PadWidths pass. Avoiding the redundant padding improves compiler/simulator performance and renders Shlw unnecessary. * [skip formal checks] Add test
2018-12-21Small convenience tweaks to IR/WIR APIs (#961)Albert Magyar
* Seal Direction trait * Add WRef factories for ports and instances
2018-11-27Add foreach as alternative to map (#952)Adam Izraelevitz
* Added Foreachers * Changed CheckTypes to use foreach * Check widths now uses foreach * Finished merge, added foreachers to added stmts * Address reviewer feedback
2018-08-07Make RemoveWires properly include registers in dependency graphJack Koenig
Fixes a bug where registers could be instantiated after nodes that referred to them Also add WRef.apply utility for nodes
2018-06-28Protobuf (#832)Jack Koenig
Add support for ProtoBuf serialization and deserialization * Add support for additional features in .proto description Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params * Add support for .pb input files This involves an API change where FIRRTL no longer implicitly adds .fir to input file names
2018-03-21GroupModule Transform (#766)Adam Izraelevitz
* Added grouping pass * Added InfoMagnet and infomappers * Changed return type of execute to allow final CircuitState inspection * Updated dedup. Now is name-agnostic * Added GroupAndDedup transform
2017-05-11Improved Global Dead Code Elimination (#549)Jack Koenig
Performs DCE by constructing a global dependency graph starting with top-level outputs, external module ports, and simulation constructs as circuit sinks. External modules can optionally be eligible for DCE via the OptimizableExtModuleAnnotation. Dead code is eliminated across module boundaries. Wires, ports, registers, and memories are all eligible for removal. Components marked with a DontTouchAnnotation will be treated as a circuit sink and thus anything that drives such a marked component will NOT be removed. This transform preserves deduplication. All instances of a given DefModule are treated as the same individual module. Thus, while certain instances may have dead code due to the circumstances of their instantiation in their parent module, they will still not be removed. To remove such modules, use the NoDedupAnnotation to prevent deduplication.
2017-05-11Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)Jim Lawson
2017-02-23move more general utils out of memutils, mov WIR helpers to WIR.scala and ↵Angie
update uses
2017-02-07Rework Attach to work on arbitrary Analog hierarchies (#415)Jack Koenig
* Rework Attach to work on arbitrary Analog hierarchies If there are zero or one Analog sources in an Attach (source meaning wire or parent module port), then the Attach will be emitted as a simple point to point connection. In the general case, alias is used for simulation while forwards and backwards assigns for synthesis. Verilator does not currently support the general case so an `ifdef Verilator `error is emitted. * Add helper functions for creating WRef from Reg and Wire
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-10-17Add fixed point type (#322)Adam Izraelevitz
* WIP: Adding FixedType to Firrtl proper Got simple example running through width inference Checks should be ok Need to look into FixedLiteral more * Added simple test for fixed types * Added asFixedPoint to primops * Added tail case for FixedType * Added ConvertFixedToSInt.scala Added pass to MiddleToLowerFirrtl transform * Replace AsFixedType with AsSInt in fixed removal * Bugfix: constant from asFixed not deleted * Added unit test for bulk connect * Fixed partial connect bug #241 * Fixed missing case for FixedPoint in legalizeConnect * Add FixedMathSpec that demonstrates some problems with FixedPointMath * Fixed test and ConvertToSInt to pass. Negative binary points not easily supported, needs much more time to implement. * Refactored checking neg widths Make checking for negative binary points easier * Added tests for inferring many FixedType ops shl, shr, cat, bits, head, tail, setbp, shiftbp * Handle bpshl, bpshr, bpset in ConvertFixedToSInt Changed name from shiftbp -> bpshl, bpshr Change name from setbp -> bpset Added more tests * Added set binary point test that fails * Added simple test for zero binary point * gitignore fixes for antlr intermediate dir and intellij dir * removed unused imports retool the fixed point with zero binary point test * simplified example of inability to set binary point to zero * Temporary fix for zero-width binary point This fix allows for all widths to be zero, but since this is a feature I am working on next, I'm not going to bother with a more stringent check. * change version for dsp tools * Removed extra temporary file * Fixed merge bug * Fixed another merge bug * Removed commented out/unrelated files * Removed snake case
2016-10-11Scala style cleanup take 5 (#324)Chick Markley
* working through variable shrouding * working through variable shrouding * working through variable shadowing * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * Fixes suggested by Adam
2016-09-25Spec features added: AnalogType and Attach (#295)Adam Izraelevitz
* Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes
2016-09-23use .head instead of (0)chick
2016-09-14fix spaces in WIR.scalaDonggyu Kim
2016-09-13use case object for WVoid, WInvalidDonggyu Kim
2016-09-13use case object for KindDonggyu Kim
2016-09-12Rework map functions as class methodsjackkoenig
Changed code from match statements in Mappers.scala to methods on the various IR classes. This allows custom IR nodes to implement the mapper functions and thus work (ie. not match error) when map is called on them. This also should have a marginal performance increase because of use of virtual function calls rather than match statements.
2016-09-07clean up WIR.scalaDonggyu Kim
2016-09-06optimize equals of WrappedExpression & WrappedTypeDonggyu Kim
2016-08-02Change serialize to abstract method on FirrtlNodeJack Koenig
2016-06-10API Cleanup - ASTJack
trait AST -> abstract class FirrtlNode Move all IR to new package ir Add import of firrtl.ir._
2016-06-10API Cleanup - PrimOp & PrimOpsJack
Add simple documentation trait PrimOp -> abstract class PrimOp Move PrimOp case objects to object PrimOps Rename PrimOp case objects to match concrete syntax Overrwrite toString for more canonical serialization Update some PrimOps utility functions
2016-06-10API Cleanup - ExpressionJack
trait Expression -> abstract class Expression Ref -> Reference abbrev. exp -> expr Add abstract class Literal UIntValue -> UIntLiteral extends Literal SIntValue -> SIntLiteral extends Literal
2016-06-10API Cleanup - StatementJack
trait Stmt -> abstract class Statement (to match Expression) abbrev. exp -> expr BulkConnect -> PartialConnect camelCase things that were snake_case case class Empty() -> case object EmptyStmt Change >120 character Statements to multiline
2016-06-10API Cleanup - WidthJack
Add simple documentation trait Width -> abstract class Width case class UnknownWidth -> case object UnknownWidth
2016-06-10API Cleanup - TypeJack
trait Type -> abstract class Type case class ClockType() -> case object ClockType case class UnknownType() -> case object UnknownType Add GroundType and AggregateType ClockType has width of IntWidth(1)
2016-05-10Added pad widths to eliminate all implicit width extendingAdam Izraelevitz
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