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path: root/src/main/scala/firrtl/Utils.scala
AgeCommit message (Expand)Author
2016-06-10API Cleanup - Field & FlipJack
2016-06-10API Cleanup - TypeJack
2016-06-10API Cleanup - Port & DirectionJack
2016-06-10API Cleanup - ModuleJack
2016-06-01Suppress "match may not be exhaustive" warningAndrew Waterman
2016-05-03Add Utils function getDeclarationjackkoenig
2016-05-03Move splitRef and mergeRef from LowerTypes to Utilsjackkoenig
2016-04-29Add time function to Utilsjackkoenig
2016-04-22Refactor LowerTypesjackkoenig
2016-04-22Add utility functions for coverting and computing Gender and Flipjackkoenig
2016-04-22Add isGround and isAggregate functions to Type Utils.jackkoenig
2016-04-22Add optional Info argument to FieldUtils.ToPortjackkoenig
2016-04-16Add Namespace for thread-safe creation of names and temporary namesjackkoenig
2016-04-14Improve performance of CSE passAndrew Waterman
2016-03-01Move mapper functions to implicit methods on IR vertices.jackkoenig
2016-02-25Separate serialize functions into separate filejackkoenig
2016-02-25Remove FlagUtils and related unused debug printingjackkoenig
2016-02-22Temporary Fix: get_type on depth=1 memories causing IntWidth(0) typesJack
2016-02-09Added license to FIRRTL filesazidar
2016-02-09Added remaining check passes. Ready for open sourcingazidar
2016-02-09CHIRRTL passes work, parser is updatedazidar
2016-02-09Added migrated HighFormCheck to Scala FIRRTL, changes to IR and Utils for get...Jack
2016-02-09Added chirrtl passes, need to update parserazidar
2016-02-09More bug fixesazidar
2016-02-09Added constprop,v-wrap,v-rename. All set to attempt like->like comparison of ...azidar
2016-02-09Added Lower Types.azidar
2016-02-09Added Expand Whens passazidar
2016-02-09Fix bug in mem serializationJack
2016-02-09Updated SInt/UInt emission to match stanza. Still need to update to new syntax.azidar
2016-02-09Fixed port emissionazidar
2016-02-09Moved passes to new packageazidar
2016-02-09Added remove accessesazidar
2016-02-09Fix serialize bugs: WSub(Field|Index|Access) printing extraneous w, module no...Jack
2016-02-09Added expand connect. Resolve now includes to working irazidar
2016-02-09Added resolve gendersazidar
2016-02-09WIP. Finished to working ir, resolve kinds, and infer typesazidar
2016-02-09WIP. Got to-working-ir workingazidar
2016-01-29Fix no space after "flip" for flipped fields in Scala FIRRTL, also make Scala...Jack
2016-01-29Changed reg syntax to new "with" semantics in Scala FIRRTLJack
2016-01-28WIP Added support for is invalid and validif to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for stop to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for printf to Scala FIRRTLjackkoenig
2016-01-28WIP: Added support for FIRRTL 0.2.0 Memories to Scala FIRRTLjackkoenig
2016-01-27WIP Moving Scala FIRRTL to match spec 0.2.0. Not everything is implemented (n...jackkoenig
2016-01-16Added notes for Richard to work onazidar
2015-12-07The transformation works! Kind of, it works fine when everything is alwasy re...jackkoenig
2015-12-03Changing simwrapper to group ports that go to different places, not quite the...jackkoenig
2015-10-15Reorganized Primops (renamed from PrimOps), added maps and functions to conve...Jack
2015-10-15Added infer-types pass, seems to work. Added infer-types error checking, modi...Jack
2015-10-14Modified getType to return Type rather than Option[Type] which makes more sen...Jack
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