| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-03-29 | Faster reg constprop (#1067) | Albert Magyar |
| 2018-02-21 | Change primop arg type (#587) | Adam Izraelevitz |
| 2017-12-12 | Refactor formal equivalence CI test | Jack Koenig |
| 2017-03-15 | Use newer rocket regression spec without comb loop | Albert Magyar |
| 2016-09-14 | Added Rob.fir for regression testing (#258) | Donggyu |
| 2016-02-25 | Remove brittle rocket comparison to expected verilog test. | jackkoenig |
| 2016-02-24 | Make rocket-golden.v match output of #75 | jackkoenig |
| 2016-02-23 | Add rocket regression, just runs rocket.fir through Verilog compiler and comp... | Jack |
| 2016-02-09 | CHIRRTL passes work, parser is updated | azidar |
| 2016-02-09 | Added rocket minus chirrtl features | azidar |
| 2016-01-28 | Update rocket regression | Andrew Waterman |
| 2016-01-23 | Update rocket regression | Andrew Waterman |
| 2016-01-16 | WIP need to correctly output readwrite ports | azidar |
| 2015-08-26 | Added regression test | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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