sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2015-07-13	Added tests for clocks. Added remove scope and special chars passes. Added ↵	azidar
	tests. Made more tests pass
2015-06-12	Major revisions to spec. Bumped to v0.1.2	azidar

2015-06-04	Fixed fir files so they correctly compile to verilog! Front-end needs to ↵	azidar
	generate as-SInt instead of convert, always. Added fast build to Makefile
2015-06-03	Fixed verilog backend bugs. Passes ALU. Fails Datapath	azidar

2015-06-02	Added sequential/combinational memories. Started debugging verilog backend. ↵	azidar
	Added Long support so UInt(LARGENUMBER) works
2015-05-29	Added custom pass. Does not correctly run, stanza just spins. Requires ↵	azidar
	debugging.
2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar

2015-05-02	Added a infrastructure for check passes, and wrote a few	azidar

2015-04-15	Finished flo backend. Restructured todo list	azidar

2015-03-24	With new stanza	azidar

2015-03-18	Finished expand accessors and lower to ground	azidar

2015-02-24	Rewrote README to include installation instructions and stanza ↵	azidar
	justification. Added response to feedback, locatd in notes/feedbackQA*. Use two different mains, one for testing and one for deployment (make build vs make build-deploy).
2015-02-20	Rewrote the initialize-register pass, now correctly implemented	azidar
	with a new IR construct - Null. LetRec is not implemented, but is marked with a TODO. Test cases for this pass are now located in test/passes/initialize-register
2015-02-19	Added compiler flags to allow tests to select which passes they test.	azidar
	Changed package names from chipper to firrtl
2015-02-18	Added more testing infrastructre, and Makefile to build firrtl	azidar

2015-02-18	Reimplemented to-working-ir. Changed Command to Stmt. Modified printing of ↵	azidar
	IR to match parser.