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AgeCommit message (Expand)Author
2019-06-13Remove unused variablesLeway Colin
2019-06-06Fix bad FirrtlStage deprecation warning (#1094)Schuyler Eldridge
2019-06-05Merge pull request #1093 from colin4124/patch-1Schuyler Eldridge
2019-06-06Fix typo.Leway Colin
2019-06-03spec: mixed-input arguments for prim ops are no longer allowed (#1085)Kevin Laeufer
2019-05-29make analog attachment order fixed with linked hash map (#1089)harrisonliew
2019-05-24Emit legal Verilog literals for ExtModule IntParams > 32-bit (#1087)Jack Koenig
2019-05-09Bugfix: GroupComponents (#1082)Adam Izraelevitz
2019-05-04Add register init to RemoveWires dependencies (#1078)Schuyler Eldridge
2019-05-04Use UnknownKind instead misrepresented NodeKind (#1076)Leway Colin
2019-04-29Merge pull request #1081 from freechipsproject/fixnodedupannotationSchuyler Eldridge
2019-04-29Update NoCircuitDedupAnnotation so it's available from firrtl.stage.FirrtlMainJim Lawson
2019-04-26Merge pull request #1005 from freechipsproject/f764.7Jack Koenig
2019-04-25Add ShellOption, DeletedWrapperSchuyler Eldridge
2019-04-25OptionsView/Viewer typeclass canonicalizationsSchuyler Eldridge
2019-04-25Add tests for Annotations/Options refactorSchuyler Eldridge
2019-04-25Add FirrtlStage, make Driver compatibility layerSchuyler Eldridge
2019-04-22Improve registered library help textSchuyler Eldridge
2019-04-22Change Memory Depth to a BigInt (#1075)Jack Koenig
2019-04-17Remove unnecessary 'FIRRTLParser' prefix (#1072)Leway Colin
2019-04-11LowerTypesSpec: additional unit test (#1071)edwardcwang
2019-04-10Remove redundant code (#1069)Leway Colin
2019-03-29Faster reg constprop (#1067)Albert Magyar
2019-03-28Merge pull request #1065 from freechipsproject/dce-printf-stopAndrew Waterman
2019-03-28Merge branch 'master' into dce-printf-stopJack Koenig
2019-03-26Convert the RemoveAccesses object into a class. (#1058)Jim Lawson
2019-03-26Add test for DCE of printf and stopAndrew Waterman
2019-03-26DCE printf and stop statements with constant-0 enablesAndrew Waterman
2019-03-25Correct a typo in spec.tex (#1063)Felix Yan
2019-03-19Designs with no SeqMems should produce empty MemConf strings, and this should...John Wright
2019-03-18Add serialization support for LoadMemoryFileType in LoadMemoryAnnotation (#1056)Jim Lawson
2019-03-07Add a data structure for memory conf reading and writing (#1041)John Wright
2019-03-05Advertise FIRRTL grammar support in AtomJean Bruant
2019-02-28Make mergify run when no reviews request changes (#1043)Adam Izraelevitz
2019-02-28[ExpandWhens] Don't create nodes to hold Muxes with >0 void cases (#1039)Albert Magyar
2019-02-27Add --nodedup option to facilitate FIRRTL to verilog regression testing. (#1035)Jim Lawson
2019-02-27Create a simple generic GraphViz renderer for DiGraph (#1034)Chick Markley
2019-02-25Run CheckHighForm after all non-emitter transforms in firrtl tests (#548)Jack Koenig
2019-02-25Detect and error on registers with flip in type (#1031)Albert Magyar
2019-02-25Merge pull request #1032 from freechipsproject/fix-scaladoc-warningsSchuyler Eldridge
2019-02-25Add GitHub source links to ScaladocSchuyler Eldridge
2019-02-25Fix almost all Scaladoc warningsSchuyler Eldridge
2019-02-22Add Width Constraints with Annotations (#956)Albert Chen
2019-02-22Stop reporting exceptions in custom transformations as internal errors (#867)Jack Koenig
2019-02-22Change mergify to just require an approval (#1030)Adam Izraelevitz
2019-02-22Bump yosys to 0.8 (#1029)Adam Izraelevitz
2019-02-21Don't let the main module become deduped out of existence. (#1023)Jim Lawson
2019-02-21No time left for you - quickly rename deep bundles still occasionally fails. ...Jim Lawson
2019-02-21Added mergify badge to README (#1027)Adam Izraelevitz
2019-02-21Added mergify configuration (#1026)Adam Izraelevitz
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