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authorSchuyler Eldridge2019-05-03 21:00:52 -0400
committermergify[bot]2019-05-04 01:00:52 +0000
commit14b9ead2ee028ba977e9c61eff962380d4e87d30 (patch)
tree3912736ea73234db1a4b5c3383506a06a9a2a45b
parent04d69d88cafa65f673cc6ef23ca1dc1f771d3be4 (diff)
Add register init to RemoveWires dependencies (#1078)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
-rw-r--r--src/main/scala/firrtl/transforms/RemoveWires.scala7
-rw-r--r--src/test/scala/firrtlTests/RemoveWiresSpec.scala16
2 files changed, 20 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/transforms/RemoveWires.scala b/src/main/scala/firrtl/transforms/RemoveWires.scala
index da79be8e..60f6cc31 100644
--- a/src/main/scala/firrtl/transforms/RemoveWires.scala
+++ b/src/main/scala/firrtl/transforms/RemoveWires.scala
@@ -90,11 +90,12 @@ class RemoveWires extends Transform {
wireInfo(WRef(wire)) = wire.info
case reg: DefRegister =>
val resetDep = reg.reset.tpe match {
- case AsyncResetType => reg.reset :: Nil
- case _ => Nil
+ case AsyncResetType => Some(reg.reset)
+ case _ => None
}
+ val initDep = Some(reg.init).filter(we(WRef(reg)) != we(_)) // Dependency exists IF reg doesn't init itself
regInfo(we(WRef(reg))) = reg
- netlist(we(WRef(reg))) = (reg.clock :: resetDep, reg.info)
+ netlist(we(WRef(reg))) = (Seq(reg.clock) ++ resetDep ++ initDep, reg.info)
case decl: IsDeclaration => // Keep all declarations except for nodes and non-Analog wires
decls += decl
case con @ Connect(cinfo, lhs, rhs) => kind(lhs) match {
diff --git a/src/test/scala/firrtlTests/RemoveWiresSpec.scala b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
index e40a770b..06e5dccd 100644
--- a/src/test/scala/firrtlTests/RemoveWiresSpec.scala
+++ b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
@@ -182,4 +182,20 @@ class RemoveWiresSpec extends FirrtlFlatSpec {
// Check declaration before use is maintained
passes.CheckHighForm.execute(result)
}
+
+ it should "order registers respecting initializations" in {
+ val result = compileBody(
+ s"""|input clock : Clock
+ |input foo : UInt<2>
+ |output bar : UInt<2>
+ |wire y_fault : UInt<2>
+ |reg y : UInt<2>, clock with :
+ | reset => (UInt<1>("h0"), y_fault)
+ |y_fault <= foo
+ |bar <= y
+ |""".stripMargin)
+ // Check declaration before use is maintained
+ passes.CheckHighForm.execute(result)
+ }
+
}