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Scala FIRRTL Compiler for chiselX
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2019-10-29
Check that all annotations provide the typeHint
David Biancolin
2019-10-29
Try implementing recursive typeHint look up
David Biancolin
2019-10-29
Change findInstancesInHierarchy to return implicit top instance
Albert Magyar
2019-10-25
Only emit the DeserilizationTypeHintsAnno when needed
David Biancolin
2019-10-24
Merge pull request #1208 from freechipsproject/comb-loop-error-info
Albert Magyar
2019-10-24
Enhance CheckCombLoops errors with connection info
Albert Magyar
2019-10-24
Add EdgeData trait to mix in to graphs
Albert Magyar
2019-10-24
Supply a trait to allow user annotations to provide SERDES type hints
David Biancolin
2019-10-22
Merge pull request #1204 from freechipsproject/else-if
Schuyler Eldridge
2019-10-22
Add Register Updates/else-if Verilog Emitter tests
Schuyler Eldridge
2019-10-22
Emit Verilog "else if" in register updates
Schuyler Eldridge
2019-10-21
Merge pull request #1202 from freechipsproject/fix-verilog-mem-delay-en
Albert Magyar
2019-10-21
Add tests for memories with latency >1, toggling enables
Albert Magyar
2019-10-21
Add library for streamlined Verilog execution tests
Albert Magyar
2019-10-21
Add test for #1179: comb-loops from VerilogMemDelays
Albert Magyar
2019-10-21
Fix write-first mem enable handling in VerilogMemDelays
Albert Magyar
2019-10-18
Upstream intervals (#870)
Adam Izraelevitz
2019-10-09
Merge pull request #1199 from freechipsproject/top-wiring-idempotent
Schuyler Eldridge
2019-10-08
Add test for TopWiringTransform idempotency
Schuyler Eldridge
2019-10-08
Make TopWiringTransform idempotent
Schuyler Eldridge
2019-10-07
Absorb some instance analysis into InstanceGraph, use safer boxed Strings (#1...
Albert Magyar
2019-10-03
Add Block factory from argument list of Statements (#1197)
Albert Magyar
2019-10-01
Restore ResolveGenders to its status as a Pass (#1192)
Jack Koenig
2019-10-01
Merge pull request #1183 from freechipsproject/mem-read-under-write
Albert Magyar
2019-09-30
Implement read-first memories in VerilogMemDelays
Albert Magyar
2019-09-30
Add read-under-write checks for memory emission
Albert Magyar
2019-09-30
Improve read-under-write parameter support
Albert Magyar
2019-09-30
Define read-write collison for independently clocked mem ports (#1188)
Albert Magyar
2019-09-30
Bump sbt to 1.3.2 (#1187)
Jim Lawson
2019-09-25
Add explicit hline instead of phantom h1 (#1189)
Schuyler Eldridge
2019-09-19
Faster inline renaming (#1184)
Albert Chen
2019-09-17
Speed up InlineInstances (#1182)
Jack Koenig
2019-09-16
Bump sbt to 1.3.0 (#1181)
Jim Lawson
2019-09-16
Merge pull request #1124 from freechipsproject/gender-to-flow
Schuyler Eldridge
2019-09-16
Update Spec from Gender to Flow
Schuyler Eldridge
2019-09-16
Deprecate Gender and add implicit Flow conversion
Schuyler Eldridge
2019-09-16
Rename gender to flow
Schuyler Eldridge
2019-09-13
Add cold benchmarking script (#1167)
Jack Koenig
2019-09-13
Update Travis stage names to match new versions (#1180)
Jack Koenig
2019-09-13
Bump Scala to 2.12.10 (#1155)
Jack Koenig
2019-09-12
Provide a name for each Travis build stage (#1174)
Schuyler Eldridge
2019-09-12
Add space, s/Github/GitHub/ in DontTouchException (#1177)
Schuyler Eldridge
2019-09-12
update inline transform and testcases
Abert Chen
2019-09-06
Refactor: remove redundancy code (#1166)
Leway Colin
2019-09-05
Filter out more filename extensions for blackbox source headers (#1134)
Albert Magyar
2019-09-05
clean up spacing in inline test
abejgonzalez
2019-09-05
Bump dependency versions (#1156)
Jim Lawson
2019-08-27
Merge pull request #1158 from freechipsproject/apoptosis
Schuyler Eldridge
2019-08-27
Add StageError
Schuyler Eldridge
2019-08-27
Add firrtl.options.ExitCode type hierarchy
Schuyler Eldridge
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