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AgeCommit message (Expand)Author
2020-01-07Switch compileFirrtlTest from Driver to FirrtlStageJack Koenig
2020-01-07Redirect testing shell commands to loggerJack Koenig
2020-01-07Merge pull request #1264 from freechipsproject/cleanup-verilog-emitter-castsJack Koenig
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
2020-01-07Remove unnecessary casts in Constant PropagationJack Koenig
2020-01-07Fix .run_formal_checks.sh skipping logic (#1297)Jack Koenig
2020-01-06Verilog emitter transform InlineNots (#1270)John Ingalls
2020-01-06Remove incorrect --firrtl-source option (#1266)Schuyler Eldridge
2020-01-06Make EmittedAnnotation Unserializable (#1288)Schuyler Eldridge
2019-12-31Merge pull request #1291 from freechipsproject/infer-resets-last-connect-sema...Jack Koenig
2019-12-30Minor code cleansup in InferResetsJack Koenig
2019-12-30Respect last connect semantics in InferResetsJack Koenig
2019-12-18Improve Scaladoc (#1284)Schuyler Eldridge
2019-12-18Fix incorrect ScalaDoc link (#1282)Schuyler Eldridge
2019-12-16{Firrtl, Circuit}Option should be Unserializable (#1278)Schuyler Eldridge
2019-12-11Make the member 'logger' added by the trait LazyLogging protected. (#1271)Jim Lawson
2019-12-06Move --no-dedup from stage-global to firrtl-local (#1265)Schuyler Eldridge
2019-12-03Logger tweaks (#1190)edwardcwang
2019-11-29Merge pull request #1258 from freechipsproject/remove-old-loggerJack Koenig
2019-11-29Remove scala-logging fully in favor of our own loggerJack Koenig
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
2019-11-19Merge pull request #1245 from freechipsproject/auto-merge-backportsAlbert Magyar
2019-11-18[Mergify] Drop review requirement for backport PRsAlbert Magyar
2019-11-18[Mergify] Automatically merge backport PRs when readyAlbert Magyar
2019-11-18Make updated type info available in VerilogMemDelays (#1243)Albert Magyar
2019-11-18Merge pull request #1231 from freechipsproject/automate-backportsAlbert Magyar
2019-11-18Merge branch 'master' into automate-backportsAlbert Magyar
2019-11-15Merge pull request #1228 from freechipsproject/getSimpleName-considered-harmfulJack Koenig
2019-11-14Use getName instead of getSimpleNameSchuyler Eldridge
2019-11-14Add test with Transform inside objectSchuyler Eldridge
2019-11-13Add spec for Analog type and attach statement (#1222)Albert Magyar
2019-11-11Add labeling to Mergify backportingJack Koenig
2019-11-11Use Mergify to automate backporting to 1.2.xJack Koenig
2019-11-07Add check for multiple sources for same wiring pin (#1191)Jack Koenig
2019-11-06Merge pull request #1206 from freechipsproject/issue-templatesSchuyler Eldridge
2019-11-06Add separate Issue and PR templatesSchuyler Eldridge
2019-11-05Move CheckResets after CheckCombLoops (#1224)Jack Koenig
2019-11-05Bump to 1.3-SNAPSHOT (#1221)Jack Koenig
2019-11-05Merge pull request #1211 from freechipsproject/serialization-utilsDavid Biancolin
2019-11-04Merge branch 'master' into serialization-utilsJack Koenig
2019-11-04Ignore extmodule instances in Flatten (#1218)Albert Magyar
2019-11-04Add explicit EOF to top-level parser rule (#1217)Albert Magyar
2019-10-31Merge pull request #1219 from freechipsproject/ifdef-initial-blockJack Koenig
2019-10-31Guard initial blocks in emitted Verilog with `ifndef SYNTHESISJack Koenig
2019-10-31Merge pull request #1216 from freechipsproject/find-instsAlbert Magyar
2019-10-30Add some simple tests to demonstrate how to provide type hintsDavid Biancolin
2019-10-29Remove an unneeded castDavid Biancolin
2019-10-29Some cleanupDavid Biancolin
2019-10-29Update src/main/scala/firrtl/annotations/JsonProtocol.scalaDavid Biancolin
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