diff options
| author | Schuyler Eldridge | 2019-10-08 14:03:14 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-10-08 14:03:14 -0400 |
| commit | 3e0abab81ef3e83425fc822e2a2dfa73fdb72ee3 (patch) | |
| tree | e4adf99f722f3da7eb86614a70214e36687448b5 | |
| parent | 357eba4c2b1549de70843899b4dae7d657757d50 (diff) | |
Make TopWiringTransform idempotent
This changes TopWiringTransform to remove TopWiringAnnotations after
it runs.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
| -rw-r--r-- | src/main/scala/firrtl/transforms/TopWiring.scala | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala index 65281382..fb6f73b4 100644 --- a/src/main/scala/firrtl/transforms/TopWiring.scala +++ b/src/main/scala/firrtl/transforms/TopWiring.scala @@ -261,7 +261,13 @@ class TopWiringTransform extends Transform { val newCircuit = state.circuit.copy(modules = modulesx) val fixedCircuit = fixupCircuit(newCircuit) val mappings = sources(state.circuit.main).zipWithIndex - (state.copy(circuit = fixedCircuit), mappings) + + val annosx = state.annotations.filter { + case _: TopWiringAnnotation => false + case _ => true + } + + (state.copy(circuit = fixedCircuit, annotations = annosx), mappings) } else { (state, List.empty) } //Generate output files based on the mapping. |
