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2020-03-12Avoid generating out-of-bounds indices in ReplaceAccessesAlbert Magyar
2020-03-11Don't const-prop a register's self-init (#1441)Albert Magyar
* Fixes #1214 Co-authored-by: Jack Koenig <koenig@sifive.com>
2020-03-11Merge pull request #1123 from freechipsproject/dependency-api-2Schuyler Eldridge
- Use Dependency API for transform scheduling - Add tests that old order/behavior is preserved Or: "Now you're thinking with dependencies."
2020-03-11Migrate to DependencyAPISchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-11Remove dead passes.DeadCodeElimination code (#1440)Albert Magyar
2020-03-10[mergify] Update match string for labeling backported PRs (#1439)Albert Magyar
2020-03-10Fix copy-paste error in DiGraph.linearize documentation (#1324)Sahand Kashani-Akhavan
Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-03-09Provide an annotation mix-in that marks RTs as dontTouch (#1433)David Biancolin
* Provide an annotation mix-in that marks RTs as dontTouch * Update src/main/scala/firrtl/transforms/OptimizationAnnotations.scala Co-Authored-By: Albert Magyar <albert.magyar@gmail.com> * Update src/test/scala/firrtlTests/DCETests.scala Co-Authored-By: Albert Magyar <albert.magyar@gmail.com> * Update src/main/scala/firrtl/transforms/OptimizationAnnotations.scala * Update OptimizationAnnotations.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-03-08Merge pull request #1429 from freechipsproject/mergify-ignore-bp-conflictsAlbert Magyar
Make mergify open backport PRs & signal on failed cherry-picks
2020-03-08Label & block conflicting backport PRsAlbert Magyar
2020-03-08Make mergify open backport PRs & signal on failed cherry-picksAlbert Magyar
2020-03-07Add firrtl-json serializers (#1430)Adam Izraelevitz
* Add firrtl-json serializers * Added support for ports, info. Added docs and tests
2020-03-06Check sign of primop constants where appropriate (#1421)Albert Magyar
* Avoid IndexOutOfBoundsException when Bits has too few consts * Check for negative consts in all relevant primops * Use BigInt for all checks on primop constants
2020-03-05Clone Verilator from GitHub, fix tag name (#1423)mergify[bot]
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-05Merge pull request #1422 from freechipsproject/revert-inline-nots-onlyAlbert Magyar
Revert inline nots
2020-03-04[skip formal checks] Emitter bugfix expected to fail LECAlbert Magyar
2020-03-04Incorporate new AddNot formal regression testAlbert Magyar
* Feedback from @jackkoening * Merge into same stage as Ops to avoid Travis delays
2020-03-04Revert "Verilog emitter transform InlineNots (#1270)"Albert Magyar
This reverts commit f77487d37bd7c61be231a8000a3197d37cf55499.
2020-03-04Remove RenameMap logging from EliminateTargetPaths (#1416)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-03Fix error message for NegWidthException (#1418)Albert Magyar
2020-03-02Update single-line when/else example in spec to match implementation (#1414)Albert Magyar
* Closes #890
2020-03-02Remove DiGraph.seededLinearize (#1413)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-02Merge pull request #1394 from freechipsproject/EliminateTargetPaths-fixesSchuyler Eldridge
EliminateTargetPaths and Unreachable Modules
2020-03-02Remove new unreachables in EliminateTargetPathsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-24[spec] clarify that div-by-zero is undefined (#1409)Albert Magyar
2020-02-21mill: add testOnly (#1408)Sequencer
2020-02-21mill: sbt-compatible publishing (#1407)Sequencer
2020-02-20Don't add ResolvePaths annotations if no targets (#1392)Schuyler Eldridge
Adds a case to CircuitState.resolvePaths such that if no targets are requested, then no ResolvePaths annotations are added. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-19Merge pull request #1357 from freechipsproject/dependency-api-updatesSchuyler Eldridge
Omnibus Dependency API Updates
2020-02-19Add optionalPrerequisites to Dependency APISchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Add dependency prettyPrint, visualization updatesSchuyler Eldridge
This adds a prettyPrint method to the DependencyManager to enable textual visualization of the TransformLikes that a DependencyManager determines need to be run. This also cleans up the GraphViz visualization with better edge coloring and now uses the `name` method when labeling graphviz nodes. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Make PreservesAll invalidates finalSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Add additional PhaseManager testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-19Support Singleton Dependencies (#1275)Albert Magyar
This makes a change to the Dependency API that breaks chisel3. This needs to [skip chisel tests], but is fixed with https://github.com/freechipsproject/chisel3/pull/1270. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-18Merge pull request #1401 from freechipsproject/reachable-from-specAlbert Magyar
Add more docs / tests for DiGraph reachableFrom method
2020-02-18Add test case for reachableFrom behavior w.r.t. including rootAlbert Magyar
2020-02-18Update reachableFrom ScalaDocAlbert Magyar
2020-02-18Revert "Repl seq mem renaming (#1286)" (#1399)Jack Koenig
This reverts commit eabc38559b7634ff7147aa0ab3d71e78558d5162.
2020-02-18Remove last connect semantics from reset inference (#1396)Jack Koenig
* Revert "Infer resets last connect semantics (#1291)" * Fix handling of invalidated and undriven components of type Reset * Run CheckTypes after InferResets * Make reset inference bidirectional on connect * Support AsyncResetType in RemoveValidIf * Fix InferResets for parent constraints on child ports * Apply suggestions from code review * Add ScalaDoc to InferResets Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2020-02-13Mill support (#1368)Sequencer
2020-02-13Update ScalaTest deprecations. (#1382)Jim Lawson
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-13Merge pull request #1361 from freechipsproject/const-prop-eqAlbert Magyar
Constant prop binary PrimOps with matching arguments
2020-02-13Add Ops equiv check to stress degenerate binary op ConstPropAlbert Magyar
* Send in the Yosys
2020-02-13Constant prop binary PrimOps with matching argumentsAlbert Magyar
* Add SimplifyBinaryOp trait * Add extra functionality to comparison folding * Add tests * Fix comments from review
2020-02-13Merge pull request #1391 from freechipsproject/instance-graph-helpersSchuyler Eldridge
Add InstaceGraph (Un)?Reachable Helpers
2020-02-13Add tests for (Un)?reachable InstanceGraph MethodsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-13Add InstanceGraph helpers: reachable/unreachableSchuyler Eldridge
Adds new APIs for querying sets of modules in an InstanceGraph: - modules: the set of all modules - reachableModules: set of modules reachable from the main/top - unreachableModules: set of modules not reachable from the main/top Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Merge pull request #1388 from freechipsproject/allow-self-renamesSchuyler Eldridge
Allow self renames
2020-02-12Add test of RenameMap not recording same renameSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Add test of RenameMap self-renamingSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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