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2021-04-05Merge pull request #2111 from chipsalliance/fpga-backendAlbert Magyar
Add -fpga flag to enable FPGA-oriented compilation strategies (currently for memories)
2021-04-05Establish a fixed relative order for FPGA-backed passes + reflect in ScalaDocAlbert Magyar
2021-04-05Add test for SeparateWriteClocksAlbert Magyar
2021-04-05Add --target:fpga flag to prioritize FPGA-friendly compilationAlbert Magyar
* Update name of FPGA flag based on Jack's comment * Add Scaladoc to describe what each constituent transform does * Add SeparateWriteClocks to --target:fpga
2021-04-05Add SeparateWriteClocks to ensure one mem write per Verilog processAlbert Magyar
* Address @ekiwi comments from review * Change match cases to scalafmt-mandated lined-up style
2021-04-05Add tests for same-address readwrite inferenceAlbert Magyar
* Update test to include both 'old' and 'new' read-under-write values
2021-04-05Allow InferReadWrite to combine shared-address R/W ports when appropriateAlbert Magyar
2021-04-05Add SetDefaultReadUnderWrite transformAlbert Magyar
* Optionally defines read-under-write behavior for all 'undefined' memories * Use DefaultReadFirstAnnotation to choose read-first default * Use DefaultWriteFirstAnnotation to choose write-first default * Seal DefaultReadUnderWriteAnnotation based on Jack's feedback
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
* This is enabled by adding a PassthroughSimpleSyncReadMemsAnnotation * Can be emitted directly with new changes to the Verilog emitter * Add some new deprecations to VerilogMemDelays * Run scalafmt on VerilogMemDelays
2021-04-05Allow direct emission of sync-read memories to VerilogAlbert Magyar
* Emit readwrite ports, if applicable * Does not change VerilogMemDelays -> no effect on default flow * Use more single-line declare-and-assign statements for mem wires * Update error messages for too-complex memories in VerilogEmitter * Run scalafmt on VerilogEmitter
2021-04-05Specify that SimplifyMems invalidates InferTypesAlbert Magyar
2021-04-04Fix mill cache download (#2171)Jiuyang Liu
2021-04-01Add memory initialization options for synthesis (#2166)Carlos Eduardo
This PR adds options for memory initialization inside or outside the `ifndef SYNTHESIS` block.
2021-03-30Fix Mill support for non-M1 Macs (#2165)Jack Koenig
* Fix Mill support for non-M1 Macs * Update build.sc Co-authored-by: edwardcwang <edwardcwang@users.noreply.github.com> Co-authored-by: edwardcwang <edwardcwang@users.noreply.github.com>
2021-03-30Update README.md (#2164)Jack Koenig
2021-03-30don't use protoc-jar anymore, mill can handle it better. (#2162)Jiuyang Liu
2021-03-29Update protobuf-java to 3.15.6 (#2136)Scala Steward
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-29Fix RemoveAccesses, delete CSESubAccesses (#2157)Jack Koenig
CSESubAccesses was intended to be a simple workaround for a quadratic performance bug in RemoveAccesses but ended up having tricky corner cases and was hard to get right. The solution to the RemoveAccesses bug--quadratic expansion of dynamic indexes of vecs of aggreate type--turned out to be quite simple and makes CSESubAccesses much less useful and not worth fixing. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-27Add NoConstantPropagationAnnotation to disable constatnt propagation (#2150)Jiuyang Liu
* add --no-constant-propagation to disable constant propagation * add test * deprecate DisableFold. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-26Fix bug in zero-width memory removal (#2153)Schuyler Eldridge
* Fix bug in zero-width memory removal Correctly remove all extraneous connections to all types of memory ports (read, write, readwrite) for zero-width memories. Previously, only read ports were correctly handled. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Fix bug in zero-width memory removal
2021-03-25add scalafmt to mill (#2151)Jiuyang Liu
2021-03-22Fix mill compile and add to CI (#2147)Jiuyang Liu
* fix for #2071 * add mill compile to CI
2021-03-19Legalize neg: -x becomes 0 - x (#2128)Jack Koenig
This fixes an error with negating a negative SInt literal and a [debatable] lint warning in Verilator when negating any value. This behavior matches that of Chisel (which directly emits the 0 - x already).
2021-03-18Ensure InlineCasts does not inline complex Expressions (#2130)Jack Koenig
Previously, InlineCasts could inline complex (ie. non-cast) Expressions into other complex Expressions. Now it will only inline so long as there no more than 1 complex Expression in the current nested Expression. Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2021-03-16Fix issue where inlined cvt could cause crash (#2124)Jack Koenig
Due to inlining of Boolean expressions, the following circuit is handled directly by the VerilogEmitter: input a: UInt<4> input b: SInt<1> output o: UInt<5> o <= dshl(a, asUInt(cvt(b))) Priot to this change, this could crash due to mishandling of cvt in the logic to inject parentheses based on Verilog precedence rules. This is a corner case, but similar bugs would drop up if we open up the VerilogEmitter to more expression inlining.
2021-03-14Fix width of constant propagation of SInt with zero (#2120)Jack Koenig
2021-03-14Fix cat of zero-width SInt (#2116)Jack Koenig
Previously, concatenating two SInts where one is of zero-width would return the non-zero-width SInt. This is incorrect because the output of Cat should be of type UInt. Now the ZeroWidth transform will introduce a cast when removing a Cat when the argument type is non-UInt.
2021-03-11Fix CSESubAccesses for SubAccesses with flips (#2112)Jack Koenig
The flow of a LHS SubAccess node may still be SourceFlow if the type of the Vec element has a flip. Tweak the logic of CSESubAccesses to check every Expression flow while recursing instead of just the flow of the final SubAccess. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-03-09Fix the readmem statements in nested block (#2109)Carlos Eduardo
2021-03-09Create annotation to allow inline readmem in Verilog (#2107)Carlos Eduardo
This PR adds a new annotation allowing inline loading for memory files in Verilog code.
2021-03-09SMT Backend: model Invalid and Division by Zero with DefRandom nodes (#2104)Kevin Laeufer
This finally removes all randomization code from the transition system conversion and into a separate pass using DefRandom nodes.
2021-03-08SMT: memory port inout fields cannot be used as RHS expressions (#2105)Kevin Laeufer
* SMT: memory port inout fields cannot be used as RHS expressions * smt: add end2end check for read enable modelling
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
With this PR the smt backend now supports memories with more than two write ports and the conservative memory modelling can be selectively turned off with a new annotation.
2021-03-04CSE SubAccesses (#2099)Jack Koenig
Fixes n^2 performance problem when dynamically indexing Vecs of aggregate types. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-03Fix ProtoBuf conversions for Verification IR (#2100)Deborah Soung
2021-03-02Remove Scala 2.11 (#2062)Jack Koenig
2021-03-02Fix CI Checks (#2097)Jack Koenig
Bumping Scala minor version but not bumping CI guards on the version causes tests to no longer run. Change to using startsWith(...) so that minor version bumps won't cause issues in the future. Also run ScalaFmt
2021-02-25Emit space after 'if' for all Verilog conditional synchronous assignments ↵Albert Magyar
(#2091)
2021-02-17ExpandWhens: ensure that statement names are maintained (#2082)Kevin Laeufer
2021-02-17Allow Side Effecting Statement to have Names (#2057)Kevin Laeufer
* firrtl: add optional statement labels for stop, printf, assert, assume and cover * test: parsing of statement labels * ir: ensure that name is properly retained * SymbolTable: add support for labled statements * test: parsing statement labels * test: lower types name collisions with named statements * ignore empty names * Inline: deal with named and unnamed statements * RemoveWires: treat stop, printf and verification statements as "others" * test: fix InlineInstance tests * DeadCodeEliminations: statements are now als declarations * CheckHighForm: ensure that statement names are not used as references * CheckSpec: throw error if statement name collides * add pass to automatically add missing statement names * check: make sure that two statements cannot have the same name * stmtLabel -> stmtName * scalafmt * add statement names to spec * spec: meta data -> metadata * EnsureStatementNames: explain naming algorithm * remove returns * better namespace use * ir: add CanBeReferenced trait * ir: add newline as jack requested
2021-02-16Merge pull request #2077 from chipsalliance/must-dedupJack Koenig
Add "Must Deduplicate" API
2021-02-16Add MustDeduplicateTransformJack Koenig
This enables marking modules as "must deduplicate". If modules marked as such do not deduplicate, the transform will create error reports and make suggestions as to why deduplication failed.
2021-02-16Add DiGraph factory method and prettyTreeJack Koenig
* New factory method enables direct construction of DiGraphs from edges * DiGraph.prettyTree enables visualization of tree or multi-tree diagraphs
2021-02-05Add file line to source link from scaladoc (#2072)John's Brew
Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
2021-02-03IR: turn some IR nodes into data classes (#2071)Kevin Laeufer
* build: add data-class dependency * ir: turn Print, Stop and Verification nodes into data classes This is in preparation to add a name field to them. Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2021-02-01Suport ir.SubAccess in Utils.splitRef (#2021)Schuyler Eldridge
* Add SubAccess case to Utils.splitRef Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Update Utils.splitRef to use IR types Change Utils.splitRef to use the actual IR types instead of their WIR aliases. Update the Scaladoc note to reflect this. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-02-01Deprecate ToWorkingIR (#2028)Schuyler Eldridge
* Deprecate firrtl.passes.ToWorkingIR Deprecate ToWorkingIR as it is now an identity transform. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Deprecate firrtl.stage.Forms.WorkingIR Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Switch from Forms.WorkingIR to Forms.MinimalHighForm Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-01ConstantPropagation: make RemoveValidIf an optional dependency (#2027)Kevin Laeufer
This allows ConstantPropagation to be used in cases where ValidIfs need to be maintained, e.g., in the formal backend. Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-28Stop padding multiply and divide ops (#2058)Jack Koenig
Fixes bug with mul or div followed by cat. Also fixes some Verilog lint issues.
2021-01-26Fix post-merge publishing (#2055)Jack Koenig
* Check Unidoc on all versions of Scala It is required for publishing and we publish every version * Fix conflicting cross-version suffixes issue When running `sbt ++2.13.4 unidoc`, SBT would set the Scala version for the fuzzer and benchmark projects even though they aren't really relevant to the command. This may be a misconfiguration or a bug in the unidoc plugin. Whatever the case, simply making it possible for them to use the same version of Scala as the firrtl project (on which they depend) fixes the issue. * Match versions of Scala in build.sbt and CI * Fix unidoc issues in 2.13.4 There is some bug in ScalaDoc not finding some links in firrtl.options so those links were made absolute as a workaround.
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