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2016-01-25Changed tests to pass with change to postfix of generated nameazidar
2016-01-25Changed first generated name to use _0 postfixazidar
2016-01-24Fixed tests that broke from changing verilog backend and removing mask from w...azidar
2016-01-24Made CInfer robust to high firrtl errorsazidar
2016-01-24Added muxing on passive aggregate typesazidar
2016-01-24Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-memazidar
2016-01-24Removed hashing as it made refchip slower to compileazidar
2016-01-24Added DefMemory to CInfer Typesazidar
2016-01-23Fix Verilog syntax errors for print/stopAndrew Waterman
2016-01-23Update rocket regressionAndrew Waterman
2016-01-23Removed buggy optimization of dshr and dshlazidar
2016-01-23Moved inst declarations after other declarationsazidar
2016-01-23Fixed commas for instances in verilogazidar
2016-01-23Added more semicolonsazidar
2016-01-23Added semicolon after assigns in verilogazidar
2016-01-23off by one error when emitting ports in verilogazidar
2016-01-23Fixed combinational read verilog backendazidar
2016-01-23Removed more prints ;)azidar
2016-01-23Removed print statementsazidar
2016-01-23Fixed bug where the write mask wasn't being generated correctlyazidar
2016-01-23Removed debugging printlnsazidar
2016-01-23Added inference to mportsazidar
2016-01-23Added prefix checker, now compliant with firrtl specazidar
2016-01-23Changed chirrtl to not require known mask valuesazidar
2016-01-22Merge branch 'new-spec' of github.com:ucb-bar/firrtl into new-memazidar
2016-01-22Added pdfazidar
2016-01-22Added a wordazidar
2016-01-22Added funding number, as well as additional acknowledgementsazidar
2016-01-22Finished version 0.2.0. Included leftovers for future user manual.azidar
2016-01-21First cut, some unfinished sections but readableazidar
2016-01-20WIP, almost finished with expressions. Removed poison, add is invalid and val...azidar
2016-01-20WIP, need to update chirrtl with new mask syntaxazidar
2016-01-20WIP: finished partial connectazidar
2016-01-19WIP: Writing new spec.azidar
2016-01-17Forgot to add the changesazidar
2016-01-17Fixed error where memory of size 1 would create an index of size 0. This can ...azidar
2016-01-17Added check for uint on access index typeazidar
2016-01-17Removed temporary filesazidar
2016-01-17BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed testsazidar
2016-01-16Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignoreazidar
2016-01-16Standard Verilog doesn't use Resolve(), but lists out the resolution passes i...azidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16Updated passes so they test new-memazidar
2016-01-16Fixed a testazidar
2016-01-16Fixed bug in lowering memories that had aggregate data typesazidar
2016-01-16Fixed bug in check-init that allows it to check on non-lowered thingsazidar
2016-01-16Moved back to create-exps instead of fast-create-exps to fix bug - fast-creat...azidar
2016-01-16Nodes must now be ground typesazidar
2016-01-16Fixed up minor errors after rebase onto masterazidar
2016-01-16Fixed Vector performance testsazidar
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