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2019-11-11Use Mergify to automate backporting to 1.2.xJack Koenig
2019-11-07Add check for multiple sources for same wiring pin (#1191)Jack Koenig
2019-11-06Merge pull request #1206 from freechipsproject/issue-templatesSchuyler Eldridge
Add separate Issue and PR templates
2019-11-06Add separate Issue and PR templatesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-11-05Move CheckResets after CheckCombLoops (#1224)Jack Koenig
Recursive literal lookup needs to be guarded against combinational loops Added a test-case to illustrate the issue when CheckResets is run before CheckCombLoops
2019-11-05Bump to 1.3-SNAPSHOT (#1221)Jack Koenig
2019-11-05Merge pull request #1211 from freechipsproject/serialization-utilsDavid Biancolin
Supply a trait to allow user annotations to provide JsonProtocol type hints
2019-11-04Merge branch 'master' into serialization-utilsJack Koenig
2019-11-04Ignore extmodule instances in Flatten (#1218)Albert Magyar
* Closes #1162 * Instances of extmodules remain in the final hierarchy * Extmodule definitions are not renamed or duplicated * The rest of the pass may proceed as normal
2019-11-04Add explicit EOF to top-level parser rule (#1217)Albert Magyar
* Fixes #1154 * Tests that #1154 example produces SyntaxErrorsException * Generally helps catch trailing syntax errors * Performance-neutral relative to previous grammar * Recommended by antlr4 devs, can help performance in some cases * See antlr/antlr4#1540
2019-10-31Merge pull request #1219 from freechipsproject/ifdef-initial-blockJack Koenig
Guard initial blocks in emitted Verilog with `ifndef SYNTHESIS
2019-10-31Guard initial blocks in emitted Verilog with `ifndef SYNTHESISJack Koenig
2019-10-31Merge pull request #1216 from freechipsproject/find-instsAlbert Magyar
Change findInstancesInHierarchy to return implicit top instance
2019-10-30Add some simple tests to demonstrate how to provide type hintsDavid Biancolin
2019-10-29Remove an unneeded castDavid Biancolin
2019-10-29Some cleanupDavid Biancolin
2019-10-29Update src/main/scala/firrtl/annotations/JsonProtocol.scalaDavid Biancolin
Co-Authored-By: Jack Koenig <koenig@sifive.com>
2019-10-29Check that all annotations provide the typeHintDavid Biancolin
2019-10-29Try implementing recursive typeHint look upDavid Biancolin
2019-10-29Change findInstancesInHierarchy to return implicit top instanceAlbert Magyar
* Change FIRRTL-internal API, affecting only one corner case * Make API more "DWIM" and consistent with other methods * Add test cases for findInstancesInHierarchy * Update Scaladoc
2019-10-25Only emit the DeserilizationTypeHintsAnno when neededDavid Biancolin
2019-10-24Merge pull request #1208 from freechipsproject/comb-loop-error-infoAlbert Magyar
Enhance CheckCombLoops errors with connection info
2019-10-24Enhance CheckCombLoops errors with connection infoAlbert Magyar
* Closes #1203
2019-10-24Add EdgeData trait to mix in to graphsAlbert Magyar
* Add Scaladoc for EdgeData API * Include stringified vertices in EdgeNotFoundException
2019-10-24Supply a trait to allow user annotations to provide SERDES type hintsDavid Biancolin
2019-10-22Merge pull request #1204 from freechipsproject/else-ifSchuyler Eldridge
Emit Verilog else-if for Register Updates
2019-10-22Add Register Updates/else-if Verilog Emitter testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-22Emit Verilog "else if" in register updatesSchuyler Eldridge
Modifies the Verilog emitter to emit "else if" blocks as opposed to more deeply nested "else begin if" blocks. This improves the output Verilog readability. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-21Merge pull request #1202 from freechipsproject/fix-verilog-mem-delay-enAlbert Magyar
Fix handling of read enables for write-first (default) memories in VerilogMemDelays
2019-10-21Add tests for memories with latency >1, toggling enablesAlbert Magyar
2019-10-21Add library for streamlined Verilog execution testsAlbert Magyar
2019-10-21Add test for #1179: comb-loops from VerilogMemDelaysAlbert Magyar
2019-10-21Fix write-first mem enable handling in VerilogMemDelaysAlbert Magyar
* Additional refactoring to clean up pass implementation * Make register names match old scheme to appease CI
2019-10-18Upstream intervals (#870)Adam Izraelevitz
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-10-09Merge pull request #1199 from freechipsproject/top-wiring-idempotentSchuyler Eldridge
Make TopWiringTransform Idempotent
2019-10-08Add test for TopWiringTransform idempotencySchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-08Make TopWiringTransform idempotentSchuyler Eldridge
This changes TopWiringTransform to remove TopWiringAnnotations after it runs. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-07Absorb some instance analysis into InstanceGraph, use safer boxed Strings ↵Albert Magyar
(#1186) * Replace instance analysis code with InstanceGraph API calls * Add convenience implicits for using TargetTokens as safe boxed strings
2019-10-03Add Block factory from argument list of Statements (#1197)Albert Magyar
2019-10-01Restore ResolveGenders to its status as a Pass (#1192)Jack Koenig
Fix minor regression from #1124
2019-10-01Merge pull request #1183 from freechipsproject/mem-read-under-writeAlbert Magyar
Implement read-first memory behavior in Verilog
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
* Corrects behavior under write collisions * Avoids heavily refactoring pass
2019-09-30Add read-under-write checks for memory emissionAlbert Magyar
* Stop ignoring read-under-write (RUW) parameter * Add conservative check: blackbox only when RUW is "undefined" * VerilogMemDelays now throws InternalError for read-first memories * Previously, read-first mems were incorrectly implemented as write-first
2019-09-30Improve read-under-write parameter supportAlbert Magyar
* Make the read-under-write (RUW) parameter typesafe * Add RUW support to the FIRRTL proto and CHIRRTL grammar
2019-09-30Define read-write collison for independently clocked mem ports (#1188)Albert Magyar
* Define read-write collison for independently clocked mem ports * Included definition of initiating write/read operation
2019-09-30Bump sbt to 1.3.2 (#1187)Jim Lawson
2019-09-25Add explicit hline instead of phantom h1 (#1189)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-19Faster inline renaming (#1184)Albert Chen
* dont chain inline and refix RenameMaps * cache already inlined modules * reduce number of chained RenameMaps * InlineInstances: cleanup and add comments
2019-09-17Speed up InlineInstances (#1182)Jack Koenig
Create instance maps once for each Module
2019-09-16Bump sbt to 1.3.0 (#1181)Jim Lawson
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