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2019-03-25Correct a typo in spec.tex (#1063)Felix Yan
2019-03-19Designs with no SeqMems should produce empty MemConf strings, and this ↵John Wright
should be parsable without excepting (#1060)
2019-03-18Add serialization support for LoadMemoryFileType in LoadMemoryAnnotation (#1056)Jim Lawson
* Add serialization support for LoadMemoryFileType in LoadMemoryAnnotation Add custom LoadMemoryFileTypeSerializer. Add test to verify LoadMemoryAnnotation can be correctly serialized/deserialized. * Simplify and focus LoadMemoryAnnotation serialization/deserialization. Respond to comments on earlier implementations. * Add type FileType definition for current chisel3 code.
2019-03-07Add a data structure for memory conf reading and writing (#1041)John Wright
* Copy MemConf.scala from ucb-bar/barstools#35 into memlib. This provides a data structure wrapper around the existing memory conf format which contains both reading and writing methods, making it easier to write code that needs to read the format. * Add MemConf tests and use a Map[MemPort, Int] for port lists instead of a Seq[MemPort] which is a bit less fragile.
2019-03-05Advertise FIRRTL grammar support in AtomJean Bruant
2019-02-28Make mergify run when no reviews request changes (#1043)Adam Izraelevitz
2019-02-28[ExpandWhens] Don't create nodes to hold Muxes with >0 void cases (#1039)Albert Magyar
* Don't create nodes to hold Muxes with >0 void cases * Added test case demonstrating void error * Memoize intermediate expression when checking for WVoid-ness
2019-02-27Add --nodedup option to facilitate FIRRTL to verilog regression testing. (#1035)Jim Lawson
* Add --nodedup option to facilitate FIRRTL to verilog regression testing. * Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.
2019-02-27Create a simple generic GraphViz renderer for DiGraph (#1034)Chick Markley
* Create a simple generic graphviz renderer for DiGraph There are three basic kinds - A simple default renderer - A ranked renderer that places nodes in columns based on depth from sources - A sub-graph render for graphs that contain a loop - Renders just nodes that are part of first loop found - Plus the neighbors of the loop - Loop edges are shown in red. * Create a simple generic graphviz renderer for DiGraph - Moved the graph loop finder into DiGraph - Fixed scala doc per Edward's comments
2019-02-25Run CheckHighForm after all non-emitter transforms in firrtl tests (#548)Jack Koenig
* Run CheckHighForm after all non-emitter transforms in firrtl tests * Remove shlw from checks.scala * Removed mistake in fix * Fix FirrtlSpec fix
2019-02-25Detect and error on registers with flip in type (#1031)Albert Magyar
2019-02-25Merge pull request #1032 from freechipsproject/fix-scaladoc-warningsSchuyler Eldridge
Fix almost all scaladoc warnings, add source links
2019-02-25Add GitHub source links to ScaladocSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-25Fix almost all Scaladoc warningsSchuyler Eldridge
This fixes all Scaladoc warnings except for those trying to link to Java. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-22Add Width Constraints with Annotations (#956)Albert Chen
* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos * add test cases * add ResolvedAnnotationPaths trait to InferWidthsWithAnnos * remove println * cleanup tests * remove extraneous constraints * use foreachStmt instead of mapStmt * remove support for aggregates * fold InferWidthsWithAnnos into InferWidths * throw exception if ref not found, check for annos before AST walk
2019-02-22Stop reporting exceptions in custom transformations as internal errors (#867)Jack Koenig
Instead, just forward the exception
2019-02-22Change mergify to just require an approval (#1030)Adam Izraelevitz
Previously would require all requested reviewers must have approved a PR before merging.
2019-02-22Bump yosys to 0.8 (#1029)Adam Izraelevitz
2019-02-21Don't let the main module become deduped out of existence. (#1023)Jim Lawson
2019-02-21No time left for you - quickly rename deep bundles still occasionally fails. ↵Jim Lawson
(#1025) * No time left for you - quickly rename deep bundles still occasionally fails. Run the "quick" calibration test three times and choose the maximum as the basis for comparison with the "deep" test. * Rename local variable to less confusing name.
2019-02-21Added mergify badge to README (#1027)Adam Izraelevitz
2019-02-21Added mergify configuration (#1026)Adam Izraelevitz
2019-02-21Prevent Flatten from stripping all annotations (#1024)Schuyler Eldridge
2019-02-21Correctly handle dots in loaded memory paths (#984)Nick Hynes
* Correctly handle dots in loaded memory paths * Added test for loadmem filename
2019-02-20Attempt to deal with timing vagaries in ↵Jim Lawson
UniquifySpec.quicklyrenamedeepbundles (#1000) * Attempt to deal with timing vagaries in UniquifySpec.quicklyrenamedeepbundles Switching to Scala 2.12.8 cause this test to start failing on OSX. Try earlier scheme to compare shallow vs deep to reduce brittleness. * Address review concerns; update comment.
2019-02-14Asynchronous Reset (#1011)Jack Koenig
Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
2019-02-11Fix typo for -c: compiler -> circuit (#1014)John Wright
2019-02-05Merge pull request #1004 from seldridge/issue-423Schuyler Eldridge
Add "mverilog" Compiler Option, MinimumVerilogEmitter
2019-02-05Do Shr constant propagation in LegalizeSchuyler Eldridge
This uses the foldShiftRight method of the ConstantPropagation Transform when legalizing Shr PrimOps. This has the effect of removing literals with bit extracts from the MinimumVerilogCompiler. This makes the formerly private foldShiftRight method of a public method of the ConstantPropagation companion object. Tests in the MimimumVerilogCompilerSpec are updated to check that Shr is handled as intended. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-05Add RemoveValidIf to -X mverilogSchuyler Eldridge
This adds the RemoveValidIf Pass to the MinimumLowFirrtlOptimization Transform. A test case is included to verify that `is invalid` is properly converted to a connection to zero. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-05Add "mverilog" and "sverilog" DriverSpec testsSchuyler Eldridge
This adds runs of the minimum Verilog compiler and SystemVerilog compiler in DriverSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-05Add "mverilog" Compiler Option, Compiler FixesSchuyler Eldridge
This adds "mverilog" to the "--compiler" command line option. This will run the MinimumVerilogCompiler. This additionally fixes the MinimumVerilogCompiler such that DeadCodeElimination will not be run (it's not supposed to be). This is done by adding a MinimumVerilogEmitter, subclassing VerilogVerilog, that strips the DeadCodeElimination step from its parent. Additionally, BlackBoxSourceHelper is removed from the MinimumVerilogCompiler since this will be run by the VerilogEmitter already. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-05Missed constprop opportunity (#1009)Andrew Waterman
* Enhance constant propagation across registers * Add more elaborate test case for register const prop
2019-02-04Correct Kind info from #1010 (#1012)Albert Magyar
2019-02-01Fork all sbt test and run tasks (#1002)Schuyler Eldridge
This avoids an apparent problem somewhere in sbt and/or scalatest where the JVM runs out of metaspace if you repeatedly run tasks. This is an annoyance for FIRRTL developers or users that keep an sbt session open. This kludges around that by forking all tasks into a separate JVM. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-01Mem helpers (#1010)Albert Magyar
* Add memory WRef factory for completeness * Refactor DefAnnotatedMemory construction for clarity
2019-01-31Use apache commons for string escaping instead of reflection (#1008)Jack Koenig
2019-01-31Add MidFIRRTL spec (#1003)Albert Magyar
2019-01-28typo fix (#1001)Sequencer
make more clear for ExecutionOptionsManager log level settings.
2019-01-26Use default test_run_dir for more DriverSpec tests. (#1006)Jim Lawson
2019-01-23Improve Shl codegen; eliminate Shlw WIR node (#994)Andrew Waterman
* Improve Shl codegen; eliminate Shlw WIR node If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's no need for Verilog-specific padding in the PadWidths pass. Avoiding the redundant padding improves compiler/simulator performance and renders Shlw unnecessary. * [skip formal checks] Add test
2019-01-22Merge pull request #969 from freechipsproject/top-wiring-aggregatesDavid Biancolin
[Top Wiring] Expand top wiring to work on aggregates
2019-01-22Merge branch 'master' into top-wiring-aggregatesDavid Biancolin
2019-01-22Bump copyright year (#999)Jim Lawson
2019-01-22Remove ghpages plugin (#996)Jim Lawson
* Remove GhpagesPlugin. (#979) * Restore old SCM reference (after removing ghpages) * Remove reference to sbt-ghpages plugin.
2019-01-21Merge branch 'master' into top-wiring-aggregatesDavid Biancolin
2019-01-15Merge branch 'master' into top-wiring-aggregatesDavid Biancolin
2019-01-14Merge pull request #992 from freechipsproject/const-prop-dshiftsJack Koenig
Constant Propagate dshl and dshr with constant amounts
2019-01-13Suppress unchecked warning in Constant PropagationJack Koenig
2019-01-13Constant Propagate dshl and dshr with constant amountsJack Koenig
Fixes #990 h/t @pentin-as and @abejgonzalez
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